SU437229A1 - Frequency divider - Google Patents

Description

The invention relates to a pulse technique and can be used in frequency synthesizers, frequency meters and other devices for dividing the frequency of periodic pulses by a fractional number of times. A frequency divider is known that contains two scaling circuits, each of which consists of a decoder with a counter connected to it with one counting input and a zero state input, two gates with two separate inputs and one output that is connected to one of the inputs of the OR element and trigger with counting input. The purpose of the invention is to provide a half-fractional frequency division multiplier. To do this, the zero state input is connected to the counter input of another counter, the zero state input is connected to the trigger input, while the same separate valve inputs are interconnected and connected to the trigger outputs, and the other gate inputs of the same name connected to the outputs of the decoders of their scaling schemes. The drawing shows a functional diagram of the proposed frequency divider. It contains scaling circuits 1 and 2, counters 3 and 4, decoders 5 and 6, gates 7-10, logic circuits “OR 11 and 12, trigger 13, input 14 and output 15. The frequency divider works as follows. In each of the decoders 5 and 6 there are two numbers each: in the decoder 5 there are numbers A and (L -) - 1), in the decoder there are 6 numbers (p-a) and a, where: L is an integral part of the required division factor ; a is the numerator of its fractional part; P is the denominator of its fractional part. The work of the frequency divider on the example of the implementation of the fractional division factor. Let the required division factor be: / C 13f-. In this case: Л 13, Л + 1 14, Рa 47-31: 16 These numbers define the basic parameters of the device. The largest of the numbers 13 and 14 is expressed in a four-digit binary number, which means that counter 3 must be four-digit. Accordingly, the decoder 5 have four inputs and two outputs

(there are only 13 and 14 numbers in it). The largest of the numbers 16 and 31 is expressed as a five-bit binary number, so counter 4 must be five-bit.

Accordingly, the decoder 6 should have five inputs and two outputs (there are 16 and 31 numbers in it).

Scaling circuits 1 and 2 work in the same way: whenever the decoder 5 (or 6) detects in the counter 3 (or 4) one of the sealed numbers (depending on which of the gates has a high potential from trigger 13) the counter 3 (or 4) is set to the zero state through the appropriate valve and the circuit "OR 11 (or 12)". The zeroing pulse from the output of the OR or (or 12) circuit is the output pulse of the scaling circuit.

Suppose that in the initial state the trigger 13 is in the single state. This means that a high potential from the single output of the trigger 13 is applied to the control inputs of the valves 7 and 8. When the pulse sequence device arrives at the input 14 of the device, the counter 3 begins to increase until the decoder 5 detects the number 13 in it. At the same time, the pulse from the decoder 5 output through the open valve 7 and the "OR 11" circuit is fed to the input of setting the zero state of the counter 3, to the output 15 of the device and to the input of the counter 4. This is repeated until the decoder 6 detects the number 16 in the counter 4. The pulse from the output of the decipher torus 6 through the open valve 8 and the OR 12 circuit is fed to the input of the zero state setting of the counter 4 and to the counting input of the trigger 13. Thus, before the trigger 13 is transferred, the zero output on the device 15 receives 16 pulses. But since each of them corresponds to thirteen inputs, then 16X13 208 pulses arrive at the input 14 of the device during this time.

After the flip-flop of the flip-flop 13 to the zero state, a high potential from its zero output goes to the control inputs of the gates 9 and 10. Therefore, the counter 3 begins to reset to the zero state upon receipt of every fourteenth pulse. At the same time, each pulse from the output of the "OR 11" output goes to the output 15 of the device and the input of the counter 4. When it detects 4 in the counter 4 of the 31 from the output of the decoder 6, the open valve 10 receives a pulse to the input of the zero state of the counter 4 and the counting input of the trigger 13. The trigger 13 is transferred to a single state.

Then all the processes are repeated. In total, during the residence time of the flip-flop 13, 31 impulses enter the output 15 of the device. But since each of them corresponds to fourteen input, then 31X14 434 impulses arrive at the input 14 of the device during this time.

A total of 208 - | -434,642 pulses go to the input of 14 devices in one cycle of operation, and

The output of the device 15 is 16-1-31 47 pulses. Division factor per cycle pa31

bots of the device is 642: 47 13-, that

47

corresponds to the required.

Subject invention

A frequency divider containing two scaling circuits, each of which consists of a decoder with a counter connected to it with one counting input and a zero state input, two gates with two separate inputs and one

an output that is connected to one of the inputs of the element OR, and a trigger with a counting input, characterized in that, in order to ensure a fractional division factor, the input of the zero setting

the state of none of the counters is connected to the counting input of another counter, the input of the installation of the zero state of which is connected to the counting input of the trigger, with one of the same separate gate inputs

combined with each other and connected to the outputs of the trigger, while the other valve inputs of the same name are connected to the outputs of the decoders of their scaling circuits.

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