SU455494A1 - Counter with 2 + 1 counting ratio - Google Patents

Description

one

The invention relates to the field of digital technology and can be used in a digital diagnostic tool. Frequencies.

A counter with a counting factor of 2 + 1 is known, containing a blocking circuit, the output of which is connected to the input of a “-disable binary counter on 1 subsequently connected counting triggers, outputs connected to the inputs of the control decoder, an additional counting trigger, one of the outputs of which is connected to the control the input of the blocking circuit, the input connected to the input of the inverter and the input thickness.

The aim of the invention is to increase speed.

To do this, in the proposed counter, the output of the inverter is connected to the control input of the control decoder, the output of which is connected to the counting input of an additional counting trigger, another output connected to the unit installation inputs of the counting trigger "-disk binary; oro counter.

FIG. 1 shows the block diagram of the proposed counter; in fig. 2-time diagram of the counter.

The counter contains a blocking circuit 1, a valid binary counter 2, a control decoder 3, an additional counting trigger 4, an inverter 5.

The counter works as follows. In the initial state, all counting triggers of counter 2 are in the state "O. At the same time at the control input of the blocking circuit. Ki / there is a single potential from the zero output of the additional counting trigger 4; On the single installation inputs of the counter 2, a "zero zero" is applied from the single trigger of trigger 4, which is not

Q affects the trigger status of counter 2.

The input locking circuits (Ii) of the input frequency are passed to the counting input of the i-bit counter 2. The counter is filled until all its

5 triggers do not return to state "1", which occurs after the first () input pulse frequency setting to state "1 first trigger of counter 2. The polling input of the decoder 3 receives the input frequency pulses inverted by inverter 5.

At the end of the input frequency () pulse at the inputs of the control decoder connected to the single outputs of the count, the 5th triggers of the counter 2, the "single potentials resolving the request of the decoder 3 are generated. A pause between the () -m and pulses (see Fig. 2), the passage through the inverter 5, interrogates the decoder 3, passes through it and sets the front edge

additional counting trigger 4 in the state "1.

At the same time, the "zero potential from the zero output of the trigger 4 closes the blocking circuit I, and the" single potential from the single arm of the trigger 4 confirms the state triggers of the discharge meter, blocking them from an accidental operation.

Impulse 2 does not change the state of counter 2, since at the control input of blocking circuit 1 there is a prohibition signal from the output of trigger 4.

The pause between and () th pulses, passed through decoder 3, switches the additional counting trigger 4, while blocking is removed from the single setting inputs of the "-discharge counter 2 and the prohibition from the control input of the block 1).

The impulse passes through the open interlock circuit / and zeroes the triggers of counter 2.

Then the cycle of the counter is repeated.

The period of the output signal taken from

of a single Ilek / rth counting trigger of counter 2, is equal to () the periods of the input sequence of countable imtguls.

Subject invention

A counter with a counting coefficient containing a blocking circuit, the output of which is connected to the input of an n-bit double counter on series-connected

counting triggers, outputs connected to the inputs of an equiphering decoder, an additional counting trigger, one of the inputs of which is connected to the control input of the blocking circuit, the input connected to the input

an inverter and an input bus, characterized in that, in order to improve speed, the output of the inverter is connected to the control input decoder input, the output of which is connected to the counting input of the smart counting trigger, another input connected to the unit set inputs of the counting trigger, one binary counter.

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Output

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Output decoder- - rator 3

Output 1 trigger

Output O

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Output

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