SU373890A1 - ALL-UNION I - Google Patents

Description

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The invention relates to the field of computing and can be used in digital computing systems.

Known frequency dividers with an odd division factor, containing a binary counter, are known.

However, these devices do not allow to use the maximum achievable speed of the counting trigger of the received element base, since they use feedback loops, which also include a low-order trigger, to ensure a given conversion factor.

In order to increase the speed in the proposed divider, the direct and inverse outputs of the first discharge trigger of the binary counter are connected to the counting input of the second discharge trigger via a switch controlled by a control and its input is connected to the output of the binary counter.

FIG. 1 yes the structural scheme of the proposed frequency divider with an odd division factor; in fig. 2 shows a detailed functional diagram of the interaction between the device for dividing the source sequence and the device for switching the pulse series; in fig. 3 is a timing diagram for a high speed frequency divider.

The frequency is divided into an odd number 2L-1 as follows.

After the division of the initial input pulse sequence into even and odd devices / division of the initial sequence (Fig. 1), the first pulse of the output sequence with the number 2L-1 will appear in the sequence of odd pulses - point 1a, which connects the first counting cycle from Hia 2N-1 input pulses by the switching device of the pulse sequences 2 to the input of the recalculating device 3 itself. When the numbering is on the order of the odd-sequence pulses as a new input sequence The sequence for the actual scaling device by the new sequence number (2L-1) of the source input sequence will be N, the pulse frequency of this new input sequence being twice the input frequency.

The actual scaling device 3 can be a common frequency divider using additional links so that the output pulse (point Z) with the sequence numbers in an odd sequence L passes the actual scaling device during the delay time on one circuit coincides, as “Through the recalculator itself, mine a chain of successively connected triggers of a binary counter.

The second output pulse in the initial input pulse sequence has the number 2 (2N-1) and, therefore, will be among the pulses of an even sequence, and its serial number in an even sequence of pulses will be 2L.

Thus, to obtain the second pulse of the output sequence at the output of the high-speed frequency divider at the point For a second counting digit, it is necessary to connect to the input of the actual scaling device 3 an even pulse sequence, which is carried out by the pulse switching device 2, the control signal for which serves as the first pulse of the output sequence.

On the next, third, counting cycle, the device for switching pulse sequences again connects an odd one to the input of the counting device 5 itself.

a sequence of pulses, the control signal being the second pulse of the output sequence, etc.

The device / division of the original pulse sequence is a common counting trigger implemented, for example, on the elements AND-NOT and is a low-order trigger of the high-speed frequency divider.

A detailed functional diagram of the interaction of the device / separation of the initial sequence of pulses with the device 2 switching pulse sequences is shown in nia. 2

Subject invention

A frequency divider with an odd division factor, containing a binary counter, characterized in that, in order to increase speed, direct and inverse, the trigger outputs of the first bit of the binary counter are connected to the counting input of the second bit through a switch, the control input which is connected to the output of the binary counter.

F input

For 3i / xffJ

entrance

FIG. one

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/ 23 2M-Z 2N1 2N 2 / r / V-rJ-J 2 / 2fJ-1j Zl2N-l 1