SU391743A1 - DECIMAL RECORDING DEVICE - Google Patents

Description

I

The invention relates to the field of automation and computer technology and is intended to recalculate the number of input pulses.

Ten (decade) scalers are known that contain a four-bit binary feedback counter.

The proposed device is characterized in that it contains an additional three-digit binary counter, the outputs of which are connected to the inputs of the decoder, and the outputs of the decoder through the OR circuit are connected to the inputs of the additional three-digit binary counter.

This makes it possible to increase the rate of recalculation of the number of input pulses.

The drawing shows a diagram of the device.

It contains a four-bit binary counter 1, an additional three-bit binary counter 2, a decoder 3, an "OR 4" circuit, an input 5 for supplying input pulses with a follow-up frequency / in, an input 6 for setting the counters to "O and an output 7.

The principle of operation of the device is to divide the input frequency by ten by separating the binary codes corresponding to each tenth pulse. A sequential series of binary codes that appear when every tenth pulse arrives at a four-bit binary counter 1 is cyclically repeated through eight code combinations. Indeed, the 10th input pulse corresponds to the code 000.1010; 20th - 001.0100; 3rd - 001.1110;

The 40th, 010.1000; 50th - 011,0010; 60-mu-011.1100; 70th - 100.0110; 80 th-101.0000; 90-mn-101.1010 and so on

This dependence is due to the fact that the smallest common multiple of 16 and

10 is the number 80 (s).

Considering that the lower bit of all codes

tenth pulses are the same and equal to “Oh, in

trigger trigger bit / can

use only one to decrypt

output phase.

Output impulses with frequency following

- removed from output 7 of the scheme "OR 4.

At the beginning of each measurement cycle (recalculation), all the triggers of the 1 to 2 counters are set to the initial state ("O).

When the input pulses arrive at input 5, the decoder 3 selects a series of states of counters 1 and 2, which are listed in the table.

Thus, on the output tires of the decoder 3, we obtain eight sequences of pulses with the following frequency,

duration shifted from / in

as a friend for a while. From release 7 of the scheme “OR 4, we will get the impulses from

a frequency of 8–, i.e., a tentative recalculation of the impulses is provided (division of the input frequency by 10).

Subject invention

Tidal counting device containing a four-bit binary counter,

the outputs of which are connected to the inputs of the decoder, the circuit "OR, characterized in that, in order to increase the speed of the device, it contains an additional three-bit binary counter, outputs

which are connected to the inputs of the decoder, and the outputs of the decoder through the circuit "OR connected to the input of an additional three-bit binary counter.