SU485563A1 - Frequency divider by 2k + 1 - Google Patents

Description

(54) BINARY COUNTER ON 2K + 1

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The invention relates to the field of automation and computer technology and can be used in the implementation of the technical means of discrete automation and digital computers.

Binary counters on 2k + 1 are known, containing fl counting triggers connected in a binary counter circuit on 4k + 2, and the inverse output of every 1, th counting trigger is connected to the counting input of the (/, +1) th trigger (where I 1 , 2, ... /), the first element And, the output of which is connected to the inputs of installation in a single state of the counting triggers of binary bits with a total weight of 2p and one of the inputs of the element OR, and the inputs of the first element And connected to inverse: counting triggers for other bits,

with the exception of the first, and with the direct output of the first-order countable trigger, the second element I.

When dividing by an odd number of upper I dungens, the frequency of dividing should be

r is half the eigenfrequency of the low trigger of the divider

The purpose of the invention is to increase the speed of the counter.

This is achieved by the fact that, in a binary counter, the inputs of the second element I are connected to the outputs of the counting triggers of binary bits with the total weight p + 1 and the inverse outputs of the other counting triggers except for the P-th, and the output of the BTOpi of the AND element are connected to the second input of the OR element.

The drawing shows the functional counter binary scheme for case K-2.

The binary counter contains an input bus 1, counting triggers 2-5, elements AND 6, element OR 7, and element AND 8. Account C-triggers 2-5 and element And 6 connect-uny according to the binary counter scheme for 4k + 2, that the output of the AND 6 element is connected to the inputs of the installation in the ED1nual state of the counting binary trigger with a total weight of 2p and to one of the inputs of the OR element 7, and the inputs to the forward output of the counting tripern of the first discharge and to the inverse trigger output 5, the element Inputs And 8 are connected to the direct outputs of the counting trigger bits of binary bits with weight p + 1 and c and the top outputs of triggers of the remaining bits, except the older one, and the output of the AND 8 element are connected to the input of the OR 7 element. The pulses of a given frequency are fed to the input bus 1. The counting triggers 2-5 and the AND 6 element form a binary counter for 4k + 2, so as with ,,,., and, therefore, the number of triggers of such a divisor P loQ r, e is equal to four. I The frequency divider of four counting triggers in the absence of feedback divides the input pulse sequence by 16 (2). In the general case, for every ten it is necessary to exclude the six states of the divisor, I The binary counter works as follows. excluded from 1 (AVSD) to 6 (AVSD) inclusive, where AVSD and the state of bits of the counters Element I 6 is triggered by the front of the skoR signal, which sets the binary to 4k + 2 to the state (AVSD), and unit inputs sets the counting triggers - 3 and 4 to state 1. The inputs of the element 6 are connected to the direct output of the counting trigger 2 of the low-order bit and the inverse output of the counting trigger of the higher bit, the special feature of such a feedback is that the binary counter at the time of the feedback is transferred from O (AVSD) to state 1 (AVSD), and thus the counting triggers 3 and 4, for the input signal effect, change their state only once. The output of the AND 6 element is connected to one of the inputs of the OR element 7, the second input of which is connected to the output of the element AND 8, the inputs of which are connected to the outputs of the binary counter triggers at 4k + 2, ..; characterizing the state of the last / removed from the state determined by the operation of the element I 6 in 2k states. The states of the described binary counter at 4k + 2 are determined by logical functions. Element 6 determines the AVSD state. Tf, the AND element 8 the AVS state fl2f. The inputs of the AND 8 junction are respectively with the outputs of the counting triggers 2, 3, and 4. The output of the metering, three1 gbr high bit counter is not connected to the input of the element And 8, which is determined by minimizing the functions of the frequency divider on 4k + 2, C outputs of the elements And 6 and 8, the counting trigger 5, respectively, you can get a signal with a frequency of 4k + 2 less than the frequency of the input signals. The frequency of the signals at the output of the element OR 7 is 2k + 1 times lower than the frequency of the input signals. masterpieces and a binary counter for 2k + 1, containing I counting triggers, connected according to the scheme of a binary counter for 4k + 2, and the inverse output of each / -th counting trigger is connected to the counting input of (L +1) -th trigger (where t 1, 2, ... P.), the first element And, the output of which is connected to the inputs of the installation in a single state of the counting triggers of binary bits with a total weight of 2p and with one of the inputs of the element OR, and the input of the first element And they are connected to the inverse outputs of the counting triggers of the remaining bits, except perth, and to the direct output ohm the counting trigger of the first bit, the second element I, different from and with the fact that, in order to increase the speed, the inputs of the second element I are connected to the outputs of the counting triggers of binary bits with the total VQOM p + 1 and inverse outputs of the other counting flip-flops, except for the N-th, and the output of the second element AND is connected to the second input of the element OR.

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