SU525249A1 - Multi-decade decade counter - Google Patents

Description

one

The invention relates to the field of computing and can be used in pulse counting devices.

Multi-decade counters are known that contain serially connected decade counters 1.

Known devices have low reliability, since they contain many counting elements.

Multi-decade decade counters containing counting decades and storage registers 2 are known.

However, these devices also have low reliability associated with a large number of countable elements.

In order to increase the reliability of the multi-digit decimal counter, the proposed device additionally introduced storage registers, delay elements, a selector, an OR element and a pulse distributor, the inputs of the registers are connected to the output of the binary-decimal counter, the outputs of the registers are connected to the inputs of the selector, the output of the selector connected to the input of a binary counter, the first outputs of the delay elements are connected to the read control input of the corresponding register, the second outputs of the delay elements dinene with control inputs for recording corresponding registers and element inputs

Or, the third outputs of the delay elements are connected to the installation input in “About a binary-decimal counter, the inputs of the delay elements are connected to the outputs of the pulse distributor, one input of the OR element is connected to the input of the device and the reset input of the pulse distributor, the output of the OR element is connected to the counting input binary” - a home counter, and an overflow output

a binary-decimal counter is connected to the input of the pulse distributor.

The drawing shows a multi-bit decade counter. The multi-decade counter contains a binary decimal counter I, storage registers 2, a pulse selector 3, delay elements 4, an OR element 5, and a pulse distributor 6, the inputs of registers 2 connected to the output of a binary decimal counter 1, the outputs of registers 2 connected The inputs of the selector 3 and its output are connected to the input of the binary-decimal counter 1, the first outputs of the delay elements 4 are connected to the read control input of the corresponding register, the second outputs of the delay elements 4 to the control write inputs of the corresponding etstvuyuschih registers and the inputs of the OR gate 5 outputs a third delay element connected to the setting input of a

"About the binary-decimal counter, the inputs of the delay elements are connected to the outputs of the pulse distributor, one input of the OR element is connected to the input of the device 7 and the reset input of the pulse distributor, the output of the OR element is connected to the counting input of the binary-decimal counter, and the overflow output of the binary the decimal counter - with the input of the distributor of pulses.

Multi-decade decade counter works as follows.

In a binary-decimal counter, pulses are counted, and in storage registers 2, the value of bits is stored. When the binary-decimal counter counts to ten and the overflow pulse occurs, the second register register is written to the counter and a unit is added, the result is written to the second register register, and the pulse count continues in the counter. If adding a unit to the contents of the second-bit register results in an overflow pulse, then the third-bit register is recorded in the counter, one is added, and the result is recorded in the third-bit register, etc.

When a pulse arrives at the device input, the pulse distributor is set to "O", a signal appears at the output of the OR element, arriving at the counting input of a binary-decimal counter, in which the pulses are counted. When the pulse counter overflow appears at the output of the distributor, a signal arrives at the input of the first delay element, and at its outputs signals appear shifted in time one relative to the other.

The first pulse from the output of the delay element reads the contents of the register of the second bit, and the information from the register through the selector is recorded in the counter. The second pulse from the output of the delay element goes through the OR circuit to the counting input of the counter, as a result of the value of the second digit is added to "1. At the same time, the second pulse from the output of the delay element 4 is fed to the control input of the register entry, allowing it to record the second bit of the counter contents. The third impulse from the output element. the delay counter is set to zero. If, by adding "1 to the value of the second bit, an overflow pulse appears, then at the second output of the pulse distributor, a signal arrives at

the input of the second delay element. The value of the third bit is added to "1, and the operation of the device occurs, as described above, only the second 5 delay element and the third bit register participate in the operations. If the addition of "1 to the value of the third bit causes an overflow pulse, then a signal appears on the third output of the pulse distributor, etc.

10 With the arrival of a pulse at the device input, the pulse distributor is set to the zero state, new values of bits are recorded in the registers, and the younger 15 bits are formed in the counter.

Claims (2)

1. USSR author's certificate No.E51325, class N OZK 23/00, 1972 2. USSR author's certificate No. 347928, class N OZK 23/00 (prototype), 1972