GB1123284A - Improvements in or relating to buffer registers - Google Patents
Improvements in or relating to buffer registersInfo
- Publication number
- GB1123284A GB1123284A GB175267A GB175267A GB1123284A GB 1123284 A GB1123284 A GB 1123284A GB 175267 A GB175267 A GB 175267A GB 175267 A GB175267 A GB 175267A GB 1123284 A GB1123284 A GB 1123284A
- Authority
- GB
- United Kingdom
- Prior art keywords
- section
- gate
- appropriate
- data
- binary element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
Abstract
1,123,284. Buffer register. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 12 Jan., 1967 [15 Jan., 1966], No. 1752/67. Heading G4C. A buffer register composed of a shift register Shaving a plurality of sections S 1 -S 5 , each of which stores a word, connected in cascade, wherein shift pulses PB are applied to each section via appropriate AND gates A 1 -A 5 is characterized by a cascade arrangement of OR gates B 1 -B 4 ,each of which is associated with a section and receives a signal indicating whether the appropriate section is empty or not, and the output of which is applied to the appropriate AND gate so that each AND gate circuit of a section preceding at least one empty section passes the shift pulses. Data from a source B can be read in to the buffer register at a variable rate and read out to source V whenever a binary element VI is set. Each section of the register S is associated with a binary element S1n-S5n which indicates whether the appropriate section is empty or not, the indications being shifted when data is shifted in the buffer register. A series of OR gates has one input connected to the appropriate binary element and one input to the output of the next preceding OR gate except gate B4 which has one input connected to binary element VI. If any section contains no data or if output is required by user V the first OR gate connected to the appropriate binary element passes a signal to enable the AND gate of the preceding section to cause data to be shifted and also causes all succeeding OR gates to pass signals causing all previous sections to shift data.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL6600550A NL6600550A (en) | 1966-01-15 | 1966-01-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1123284A true GB1123284A (en) | 1968-08-14 |
Family
ID=19795482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB175267A Expired GB1123284A (en) | 1966-01-15 | 1967-01-12 | Improvements in or relating to buffer registers |
Country Status (4)
Country | Link |
---|---|
DE (1) | DE1283284B (en) |
FR (1) | FR1507949A (en) |
GB (1) | GB1123284A (en) |
NL (1) | NL6600550A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3643221A (en) * | 1970-04-16 | 1972-02-15 | Ibm | Channel buffer for data processing system |
NL7713707A (en) * | 1977-12-12 | 1979-06-14 | Philips Nv | INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH VARIABLE INPUT AND FIXED OUTPUT. |
DE3213345C2 (en) * | 1982-04-08 | 1984-11-22 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Data transmission device between two asynchronously controlled data processing systems |
-
1966
- 1966-01-15 NL NL6600550A patent/NL6600550A/xx unknown
-
1967
- 1967-01-11 DE DE1967N0029804 patent/DE1283284B/en not_active Withdrawn
- 1967-01-12 GB GB175267A patent/GB1123284A/en not_active Expired
- 1967-01-16 FR FR91219A patent/FR1507949A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE1283284B (en) | 1968-11-21 |
NL6600550A (en) | 1967-07-17 |
FR1507949A (en) | 1967-12-29 |
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