DE1283284B - Buffer register - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int CL:

GlIc

German class: 21 al - 37/64

Number: 1283 284

File number: P 12 83 284.7-53 (N 29804)

Filing date: January 11, 1967

Opening day: November 21, 1968

Buffer register

The invention relates to a buffer register which is a shift register with a number in cascade contains switched sections, the input information is supplied from the output is transferable to a consumer, and depending on the fact whether certain sections are empty or not, shift pulses are fed to the sections via "and" gate circuits will.

Such registers are used for the temporary storage of information, especially for the Case that information is offered to a consumer at irregular times, with temporary the speed with which the information is supplied is greater than the current consumer can handle.

In general, such buffer registers are cascaded as a multiple shift register executed switched sections in each of which a word can be recorded. To a to utilize large buffer capacity and to achieve that information is always available to the consumer stands as long as there is still information in the register, it is desirable that the information is always postponed in such a way that any empty sections in between are filled as soon as possible and maintain an uninterrupted series of information at the end of the register will.

In a known circuit arrangement, depending on the fact whether certain sections are empty or not, the sections of a shift register via "And" gate circuits shift pulses supplied, in such a way that these pulses only in those lying at the beginning of the cascade connection Sections which precede the first empty section in the sliding direction take effect. the Gaps are thus filled in from the front, which means that empty, further back lying sections should only be completed after all of the preceding sections have been completed so that there is a possibility that no information is available to the consumer, although the latter is probably in the register.

In other known circuit arrangements, a comparison circuit is assigned to each section, which compares the status of the relevant section with that of the next following section and generates a shift pulse if information is provided in the relevant section and in the next following Section no information is available. Such a comparison circuit is not only proportionally

Applicant:

N. V. Philips' Gloeilampenfabrieken,

Eindhoven (Netherlands)

Representative:

Dr. Herbert Scholz, patent attorney, 2000 Hamburg

Named as inventor:
Christianus Antonius Lammers,
Gerardus Johannes Jacobus Moonen,
Emmasingel, Eindhoven (Netherlands)

Claimed priority:

Netherlands of January 15, 1966 (6 600 550) - -

moderately intricate and expensive, but there is also the disadvantage that the circuit is relatively works slowly because information is pushed on from one section to a following section can only take place when the following section has really become empty, so that with in other words, an uninterrupted series of information not entirely and at the same time can be pushed further.

The invention provides a simple and convenient solution to the problem.

According to the invention, »Unde gate circuits over a number of cascaded and assigned to the different sections "Or" gate circuits controlled, with an input of these gate circuits depending on the Fact whether the associated section is empty or not, a signal is supplied in such a way that every “and” gate circuit of a section preceding at least one empty section the Lets pushing impulses through.

The invention is described below with reference to the schematically depicting an exemplary embodiment Drawing described.

The buffer register contains a number of memory sections S ₁ to S ₅ , which are connected in cascade and are set up in a known manner such that when a shift pulse from the shift pulse source PB is fed to the control inputs SS ₁ to SS ₅ , the information from this section is transferred to the next section is transferred. If those

809 638/1499

If pulses were fed to all sections, the information would be shifted one place to the right in an uninterrupted series. Each section consists of a number of subsections such as: B. S ₁₀ , S ₁₆ , S _{1 c} , so that multiple binary information, ie a word, can be recorded in each section. The number of sections and subsections is basically arbitrary. With each pulse of the pulse source PB , new information originating from an information source B can in principle be written into the first section S ₁ and information from the last section S ₅ can also be passed on to the consumer V for further processing. The number of pulses supplied per second by the pulse source PB is, however, much greater than the number of words that the consumer F can process per second. The transmission of information to the consumer therefore only takes place when the consumer V asks for it, which will generally be the case at regular points in time, so that the information is processed by the consumer at maximum speed. On the other hand, new information can generally be offered to the shift register from source B at irregular times, in such a way that ζ. Β. a number of new words are offered in quick succession, followed by a pause. Of course, the number of words offered must not be greater on average than the number that the consumer can process on average, and the capacity of the register must not be exceeded either.

The shift pulses from the pulse source PB are fed to the sections via separate "And" gates A ₁ to A ₅ . Each section is also assigned a binary storage element, S _2n , S _sn , S _in and S _5n , the storage state of which is indicative of the presence or absence of information in the associated section. These memory elements are combined in a corresponding manner to form a shift register and also receive shift pulses from the gates A ₁ to A ₅ , so that the information in the memory elements S _1n to S _{5n is} shifted in the same way as in the sections S ₁ to S _5. When new information is written into the first section S ₁ , a binary “1” is written into the element S _1n via the source B at the same time. The consumer V is assigned a binary element V _n , which is led to the state "1" if the consumer V wishes to receive information from the section S _5.

The elements S _1n to S _5n and V _n are connected to inputs of “Odere circuits B ₁ to 5 ₄ , which are connected in cascade and whose outputs control the“ And ”gates A ₁ to A ± . The element V _{n also} controls the gate A ₅ . This circuit is such that, if a section contains no information, the associated element S ₂ " to S _{5 n} sends a signal to the" and "gate each in the sliding direction of the empty section via the cascaded" or "gates the previous section, whereby this "and" gate allows sliding impulses through. If the consumer V wishes to receive information, all "and" gates are opened via the element V _{n and the mentioned cascade connection.}

Conversely, an “and” gate A ₁ to A ₅ is also open and the shifting pulses are passed on to the associated section if at least one section following the section in question is empty and / or if the consumer can receive information. The information in the part of the shift register preceding the last empty section is then completely shifted with each pulse, so that the information in the rear part of the shift register is combined to form an uninterrupted row.

Claims (1)

Claim: Buffer register, which contains a shift register with a number of cascaded sections, wherein the input information is fed from the output to a consumer is transferable, and depending on whether certain sections are empty or shift pulses are not fed to the sections via "and" gate circuits, thereby indicated that the "and" gates via a number of cascaded and the "or" gate circuits assigned to the different sections are controlled, one input of these gates depending on whether the associated Section is empty or not, a signal is supplied in such a way that every "and" - Gate circuit of the at least one empty section preceding sections the shift pulses lets through. 1 sheet of drawings 809 638/1499 11.68 © Bundesdruckerei Berlin