SU606210A1 - Frequency divider with variable division coefficient - Google Patents

Description

(54) FREQUENCY DIVIDER WITH VARIABLE COEFFICIENT

Fission

The device contains a decade counter 1, the element AND 2, necessary for expanding the J-inputs of the output 3 and commuting 4 trig hero; I-NE elements 5 of the initial state setup, one inputs of which are connected with the corresponding outputs of the coding unit 6, the second inputs - with the output of the trigger 3 and with the reverse transfer chain of the high decade of the counter. The outputs of the first and second elements AND-NOT 5 are connected respectively to the S-inputs of the second and third triggers of the counter 1, the output of the third element AND-NOT 5 - to the J-input of the fourth trigger.

In the initial state, the triggers of the counter G are in the position corresponding to the number n 9 - N, where N is the division factor of the decade of the unit of units.

Since the fourth trigger of the decade counter 1 switches to one state not from the eighth input pulse, but from the scratch. Go, decimal numbers (p) 6 and 7 are written to the counter as binary numbers 1110 and 1111.

Triggers 3 and 4 are in zero position in the initial state. A low level of trigger output 3 through an AND-HE element 5 provides high voltage levels at the S outputs of the second and third triggers, and the inverse output of trigger 4 provides a high voltage level at the J input of the first trigger.

The low level of the reverse transfer circuit provides high levels of voltage through the AND-HE 5 element at the J-input of the fourth trigger and through the And 2 element at one of the three logic-connected And J-inputs of the flip-flops 3 and 4.

Counter 1 is filled as follows. Each input pulse arriving at the C input of the first trigger changes the state of the counter. In each decimal counting cycle, the generous (1110) state of the counter is accompanied by the appearance at the output of a fourth high level trigger, the zero (00) state — the occurrence of a low level.

The transfer pulses formed in this way have a duration of 4TDD, which corresponds to a duty cycle of 2, 5. Consequently, the speed requirement of the older decade of the counter compared to the first one can be reduced eight times.

When the older decade of the counter is filled, a high voltage level occurs in the reverse transfer circuit, and the counter continues the last counting cycle. Under the influence of the sixth input pulse of the last counting cycle, the fourth trigger, depending on the code combination of the number being written, either switches to the one state or remains in the zero state. With the division factors O, 1, 2, 3 at the output of the high bit of block 6, the voltage level is low, so a high level at the output of the corresponding AND-HE element 5 does not prevent the fourth trigger from switching to one state. In other cases, this output of block 6 is a high voltage level, which coincides with a high voltage level of the reverse decade transfer circuit of the senior decade, and a low voltage level is formed at the output of the AND-HE element 5. By entering one of the J-inputs connected by the AND logic, this low level prevents the fourth trigger from being switched to the one state. After the impact of the seventh input pulse of the last counting cycle, the first three triggers are in a single state, as a result of which high voltage levels are set at all J inputs of triggers 3 and 4. The eighth input pulse switches the first three triggers to the zero state, and the trigger 3 to the single state. Trigger 4 either also switches to a unit if the division ratio of the first decade (unit of units) is odd and at the output of the lower unit of block 6,

5 and therefore at the R input of the trigger, a high voltage level. With an even division ratio, trigger 4 remains in the zero state.

The ninth input pulse of the last counting cycle returns trigger 3 to the zero state. The short high voltage level at the output of the trigger 3 is equal to the duration of the period of the input signal and is the output signal of the divider. This impulse, arriving at the inputs of the AND-NE 5 elements, sets the initial state of the second and third flip-flops in accordance with the code combination coming from block 6 to the second inputs of the AND-NOT 5 elements.

The ninth input pulse sets the first trigger of the first decade of counter 1 to its original state. If the division factor of this decade is even, a high voltage level is present at the J-output of the first trigger, and the ninth input pulse sets it to one. With an odd division factor at the J input of the first trigger, the voltage level is low, so the first trigger remains in the zero state, and the switching trigger 4 returns to the zero state.

At this point, the work cycle of the divider is completed.

The steady state operation of the circuit is to repeat these cycles.

Claims (2)

1. USSR author's certificate №, N 03 K 23/02, 72. 2. USSR author's certificate No. 609999, H 03 K 23/00, 1974 .. 1Start , aenoT