SU1422403A1 - Counter - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to expand the functionality of the counter. The counter contains N registers 1, where N is the degree of the forming polynomial, K groups 2 multiplication blocks 3, K blocks 4 divisions, K blocks 5 addition, where, and element 6. 6. Introduction n blocks 9 addition, where, and the formation of new functional links provide the meter with the ability to count on any module not exceeding L, and increase its reliability. 4 il. about

Description

Phage.G

The invention relates to a pulse technique and can be used in automation and computing devices,

The aim of the invention is to enhance the functionality by enabling the counting of any module not exceeding L and increasing the reliability.

Figure 1 is a block diagram of a counter; in Fig. 2. - example of a counter for L 5, K 1; in FIG. 3, the table of correspondences of the elements of the GF (5) field of the register-pressing registers; in FIG. 4, the transition table of the device;

The counter (Fig. 1) contains 5 N registers 1, where N is the degree of the forming polynomial, K groups 2 multiplication blocks 3, K divisors 4, K first addition blocks 5, where 16 K6N, And 6, whose output connected to the corresponding inputs of the last groups of inputs of the K-first addition blocks the remaining groups of platoons. Through the corresponding multiplication blocks of the corresponding groups are connected to the outputs of the corresponding powerful registers j outputs To the first addition blocks 5 through the corresponding 4 division blocks are connected to the information inputs of the first To Registers, and clock adjusting vhbdy registers respectively connected to a clock 7 and 8 ustanonochnym counter inputs. Device

It also contains the second plots 9 of the add, where O p 6 (NK), the output of the element I is connected to the corresponding - inputs of the first groups of inputs of the second blocks of complex, the second groups of inputs of which are connected to the outputs of the corresponding registers, the outputs of the second blocks The additions are connected to the information inputs of the respective subsequent NK registers, the inputs of element 6 I are connected to the outputs of the registers.

The counter works as follows.

The number of registers of the counter N. is determined by the degree of the generating polynomial whose coefficients belong to the Galois field of L elements, where L is the power of a prime number, the degree of the forming polynomial is determined, in turn, by the counter module and is found in the expression M L,

The basis of the counter is the genera- tor of the L-oriental pseudo-random targets.

0

five

0 5 0

five

five

Q

l

Ice length, which includes registers, multiplication blocks, addition and division in the Galois field of L elements GF (L). The initial data for designing the generator itself are L, K, N, F (x), where L is the power of a prime number, K O is an integer, N is the power of the generating polynomial F (x), primitive over GF (L).

The generator operates in accordance with the equation

Q (t n- 1) Q (t) .T

where Q (t) and Q (t + 1) are vectors characterizing the state of the generator registers at times t, and t + 1, respectively, {T is a square matrix of order N, whose form is uniquely determined by the constituent polynomial

F (x) atsh ... a; x + ... a, x + + a „, a, -, a„ € GF (L).

. The generator consists of N registers, the width of which is equal to R log.L (the value of R must allow binary numbers from O to L-1). The generator also includes K blocks of addition (BS) in the field GF (L), K blocks of division in the field of GF (L), K groups of multiplication blocks (BU) in the field of GF (L). The values by which multiplication and division occur in the corresponding CU and DB are uniquely determined by the type of the accompanying matrix T. At K 1 (Fig. 1), the magnitude by which the multiplication occurs in iM CU, i 1, N, is equal to the corresponding coefficient but; the generating polynomial F (x), the value by which the division occurs in the division block (DB) is equal to HQ, where af is the free term of F (x). BS, CU and DB are combinational circuits that are based on the corresponding truth tables, which, in turn, are uniquely determined by the rules of addition, multiplication and division in the GF (L) field, and also the correspondence between the elements floor and register contents generator

ra. With L 2, where P O is the whole, these blocks are easily realized on

We simulate (L - M) cycles of operation of the generator corresponding to F (5s) with the initial state Q (0) Q, (0) ... Q, (0) ... QM (OII a ... a .. a where ae GF (L), i 1, N.

We define the state Q (L - M) Q, a - M) ... Qi (L - M) ..-. Qf, (L - M) b ... b; ... b, the N-K of the second BS is entered in the Stone box and the elec- tor should go over the generator from the AND, a. also new connections. Each state, o. a .. and gf (l). of K first BS in the most difficult case- We build a counter in accordance with

modulo two. In more complex cases: their cases are possible on the basis of ROM. In the latter case, the ROM boot map is again uniquely determined by the rules of execution of the corresponding operations.

To build a counter for an arbitrary module M in the device

when all the coefficients a ;, are different from zero, it has N + 1 groups of inputs, and in each group of R-inputs. A part of the inputs of the last group of inputs of the first and second BSs (the second BSs always have two groups of inputs) is connected to the output of element I.

Z is a signal that takes a single value.

20

if the generator is in the condition

g -1

a, ... a; ..., where a is an element

GF (L), which corresponds to the code

The remaining N input groups of the first add-on blocks are connected to the outputs of the corresponding registers via the corresponding control units. Each of the multiply and add blocks has R inputs.

and R-outs. If the corresponding code is 25 all units, C GF (L) is the effect of a; forming a polynomial of equalities m is equal to 1, then the i-th BU implements intelligent C; + Y a-, a-, living on 1, which is equivalent to simple where a :; - elements of the signal transfer from the inputs to the outputs. Thus, the necessary module of the CU is unchanged. Similarly, if the conversion recalculation zone is provided by pro- ation 1, then the corresponding DB is also started by the generator of some of its own simple signaling.

Figure 2 shows an example of a specific change in counter implementation for the case of M -

In order for the output of the element 3g 23, L 5, F (x) 3x + x + 4 And the signal log to appear. one

one of the elements of the floor GF (L) must

represented as a combination of all

units. Specific match type

between the elements of the GF (L) field and the content of 40 of FIG. 3, one of the possible visible registers is shown in no way influences the correspondences of the GF elements (5)

primitive over t5F (5), K 1.

The basis of the counter is a generator of a five-dimensional pseudo-random post-

VN

values of length L - 1 24. On

structure and character of the functioning of the device. With L 2, the combination of all units automatically corresponds to one of the elements of the GF (2P) field.

The algorithm for constructing a synchronous counter for a given module M has the following form.

Based on the inequality L%; M is selected by a polynomial F (x) of degree N, primitive over GF (L).

If M L 1, then go to step 45 of the generator sequence (which is equal to the number of states of the generator registers), the device must be able to skip one state of registers, namely

50 either, which immediately follows the 4.4. Simulation of L - M 2 clock cycles of the generator allows to determine the state that should be skipped - 1 4J, and

PG b, otherwise, the synthesis of the 55 state in which must go

generator from state 4 4j - Sz O. From here you can find

The counter is reduced to constructing, according to well-known rules, an L-triple sequence generator of length L or L - 1.

The terms C and C, which must be submitted to the appropriate groups

by equation

Q (t + 1) Q (t) -T + 7, -C, where C, c, ... Cj ... CM,

C is the L-number that comes to the corresponding group of inputs i-ro BS, when the signal is Z 1;

Z is a signal that takes a single value.

if the generator is in the condition

g -1

a, ... a; ..., where a is an element

GF (L), which corresponds to the code

 23, L 5, F (x) 3x + x + 4 primitive over t5F (5), K 1.

The basis of the counter is a generator of a five-dimensional pseudo-random post-

VN

values of length L - 1 24. On

and the state of the generator registers and

- -,

a, a.2. 4. as required unit of recalculation on unit less than the period

45 generator sequences (which is equal to the number of states of the generator registers) —in the device, it must be possible to skip one state of registers, namely, the state that immediately follows state 4.4. Modeling the L - M 2 generator clock ticks allows the state to be skipped - 1 4J, and

The terms C and C, which must be submitted to the relevant groups

in; BS; so that when z 1 (z 1 when registers 2 and 2j are in state 4 4), the device registers from state L 4 immediately went to state L3 1J, skipping state l 4 . C, 2. (. 2, In order for the corresponding BS inputs at z I to be given code 2-101

(FIGOZ), you need the first and third. 10 no, where, element And, output

Bho, g, s of the corresponding inputs should be connected to the output of the element I, at the output of which a signal z is formed, and the others corresponding to the pgne O in the representation of the number 2, i.e. The second, subordinate, groups of groups are connected to the output bus to the log bus, O (figure 2). With

Ь 2 or BS-based ROM implementations with L - 2 connect the inputs corresponding to O to the O bus

in the representation of numbers. C, there is no need for 20 P registers, clock and set points

Dietstio Figure 1 shows only the connections of some of the inputs of the corresponding groups of BS inputs with the outputs of the element And „

One of block 3 (multiplication, multiplying by a, 1, and block dividing j by dividing by -4 1 (FIG. 2) 5) shows how to perform simple inputs of the first groups of inputs of the second

I send signals from my inputs to outputs without change.

addition blocks, the second groups of inputs of which are connected to the outputs of the corresponding previous registers, the outputs of the second addition blocks are connected to information inputs of the corresponding

The equations of counter counts by mod. 23 (fig2) have the form ...

fQ, (t -: - 1) Q, (t) +. ) + z-2 (mod 3); , the subsequent (N-K) registers, Q, (t + 1) CQ, (t) + z-2 (mpd5).

where Q; (t) and Q | - (t + 1) are the contents

The inputs of the And element are connected to the BbUCtjAaM registers.

L

1-4-5-WLJ

Claims (2)

The i-ro register at times t and t + 1, respectively, i 1, 2. The formula of the invention A counter containing N registers, where N is the degree of the forming polynomial, K groups of multiplication blocks, K division blocks, K first blocks of which are connected to the last group of inputs K first blocks of addition, the remaining groups of inputs of which, through corresponding blocks of multiplication, correlate the corresponding registers Outputs To the first blocks of addition through the corresponding blocks of division are connected to the information inputs of the first To the inputs of the registers are connected, respectively, with the clock and installation inputs of the counter, characterized by the fact that, in order to expand the functionality and increase reliability, it additionally contains n second addition blocks, where O i p (NK), and the output of the element And connected with the corresponding addition blocks, the second groups of inputs of which are connected to the outputs of the corresponding previous registers, the outputs of the second addition blocks are connected to information inputs of the corresponding subsequent (N-K) registers The inputs of the And element are connected to the BbUCtjAaM registers. FIG. four