RU1829028C - Generator of orthogonal signals - Google Patents

Abstract

The invention relates to automation and computer engineering and can be used to obtain a new class of integral (piecewise linear) orthogonal signals. The aim of the invention is to expand the functionality by forming a complete orthogonal system of integrated signals. The goal is achieved in that the generator contains a clock, two groups of adders modulo two, integrators and multipliers. A complete orthogonal system of integrated variable signals is taken from the outputs of the generator. 2 ill.

Description

The invention relates to the field of automation and computer engineering and can be used to obtain a new class of integral (piecewise linear) orthogonal signals.

A new class of integrated orthogonal signals is obtained as follows. Consider the usual Walsh signals. To begin with, we take the complete system of sixteen Walsh signals, which in the + and - symbols have the form:

++ + + + + + + + + + + + + + + +

++ + + + + + + - ----- -

++ + + ---- + + + + + --- ++ + + - - - ---- + + + +

++ - - + + - - + + - + n

++ - + + ---- + + - + +

++ - - - - + + + + + - - - - + +

++ ---- + + - + + + + - + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + - +

+ - + - - + - + + - + - + - +

+ - + + - - + + - - + + - - +

+ - + - + - + - + - + + - + - + - + + - + - + + - + + i I1 Л I1 1

I 1P -j- -. -j- -u

+ - + - + + - + + - + - +

We leave the signal a) о as it is. And in the remaining fifteen signals, we replace the smallest discrete with a triangular signal; moreover, if the signal is positive at a given discrete, then it corresponds to a triangle with its top up, and if it is negative, then its top is down. Thus, we obtain the set of sixteen signals presented in FIG. 1. It is straightforward to verify that the resulting population is orthogonal. Due to the fact that each Walsh signal is associated with a piecewise linear (integral) signal, the signal system obtained in this way is complete.

The aim of the invention is to expand the functionality of

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th

a torus consisting in the possibility of forming a complete orthogonal system of integrated signals.

This goal is achieved in that in an integrated orthogonal signal generator comprising a clock, a counter, four adders modulo two first groups, a first integrator, four multipliers, the clock output being connected to the counter input, i-ro and (i + 1 ) -ro bits (, 2,3,4) which are connected to the inputs of the i-ro adder modulo two first groups, contains second to fourth integrators, two adders modulo two second groups and fifth to eleventh multipliers, and k- (, 2,3) the group of multipliers ω It holds a 2k-1 multiplier, the first inputs of which are connected to the outputs from the second to fourth integrators, the outputs from the first to fourth integrators are connected to the outputs of the respective adders modulo two of the first group, the outputs of the first and third bits of the counter are connected to the inputs of the first adder by module two of the second group, the output of which is connected to the first input of the second adder modulo two of the second group, the second input of which is connected to the output of the second digit of the counter, the second inputs of the j-ro multiplier of the k-th group) is connected to the output In the case of j-ro counter bits, respectively, the second inputs of the third multipliers of the second and third groups are connected respectively to the output of the first adder modulo two of the first group and the output of the fourth bit of the counter, the output of the third bit of which is connected to the second input of the fourth multiplier of the third group , the second inputs of the fifth, sixth and seventh multipliers of which are connected respectively to the output of the first adder modulo two of the first group and the outputs of the first and second adders modulo two of the second group, outputs integ Ator and all the multipliers are generator outputs.

In FIG. 1 shows orthogonal signals; in FIG. 2 - generator of integrated orthogonal signals.

It contains a clock 1, the output of which is connected to the input of a five-digit binary counter 2, adders modulo two 3, integrators 4 and signed multipliers 5. In this case, the outputs of the bits of the counter 3 are connected to the inputs of four adders modulo two 3 so that the i-th and (1 + 1) -th (i-1,2,3,4) outputs of the bits of the counter 2 are connected respectively to the first and second inputs of the i-ro adder modulo two 3, the outputs of which are connected to the inputs of four , integrators 4, In addition, there is an additional group of adders modulo two, containing two additional adders modulo two 3. In this case, the first input of the first one is connected to the output of the first bit of counter 2, and the second input is connected to the output of the third bit of the same counter. The first

0 the input of the second adder modulo two 3 is connected to the output of the first adder modulo two 3, and the second input is connected to the output of the second bit of counter 2. The outputs of all integrators 4, except the first, are connected to the inputs of three groups of signed multipliers 5, In this, in the first group of symbolic multipliers, there is one symbolic multiplier 5, in the second three, in the third seven. The second input of the sign multiplier 5 of the first group of sign multipliers is connected to the output of the first digit of counter 2. The second output of the second sign multiplier 5 of the second group of sign multipliers is connected to the output of the second digit of counter 2. The second input of the third sign multiplier 5 of the second group of sign multipliers is connected with the output of the first adder modulo two 3 of the main

0 groups of adders modulo two. The second input of the first sign multiplier 5 of the third group of sign multipliers is connected to the output of the first digit of counter 2. The second input of the second sign multiplier 5 of the third group of sign multipliers is connected to the output of the second digit of the counter 2, The second input of the third sign multiplier 5 of the third group of sign multipliers is not connected with the output of the fourth digit of counter 2. The second input of the fourth signed multiplier 5 of the third group of signed multipliers is connected to the output of the third digit of counter 2 The second input of the fifth sign multiplier 5 of the third group of signed multipliers is connected to the output of the first adder modulo two 3 main groups, adders modulo two. The second input of the sixth signed multiplier 5 of the third group of signed multipliers is connected to the input of the first adder modulo two 3 additional groups of adders modulo two. The second input of the seventh significant multiplier 5

5 of the third group of symbolic multipliers is connected to the output of the second adder modulo two. 3 of the additional group of adders modulo two. The outputs of 6,7,8,9 integrators and 10-20 sign multipliers are information outputs of the generator of integral orthogonal functions.

The generator operates as follows.

At the time of operation, the clock pulses from the output of the clock generator 1 are fed to the input of the counter 2, which starts generating Rademacher signals RI, R2, Rs, R4 and RS, which, respectively, are coupled to the inputs of the adders modulo two 3 of the main group of adders modulo two. From the outputs of the adders modulo two, the Walsh signals are removed, which, after integration, go to the outputs of the integrators 4. As a result, the outputs 6,7,8 and 9 of the integrators 4 produce the second, third, fifth and ninth integral signals, respectively (see Fig. 1). The third integral signal, taken from output 7, is fed to the first input of the sign multiplier 5 of the first group of sign multipliers, the second input of which receives the Rademacher signal RL. As a result, the fourth integral signal is received at output 10 of the sign multiplier 5 (see Fig. 1, position 4). The fifth integral signal from output 8 is supplied to the first inputs of the sign multipliers 5 of the second group of sign multipliers, the second inputs of which respectively receive Rademacher signals Ri, Ra and RiR2, as a result of which their sixth, seventh and eighth outputs the integral orthogonal signals shown in FIG. 1 in the corresponding positions. Similarly, the ninth integral signal is supplied to the first inputs of the sign multipliers 5 of the third group of sign multipliers, the second inputs of which receive signals Ri, R2, R3, R4, RiR2, R2Rs, RiR3, RiR2Rs. As a result, the remaining missing integral signals are removed at outputs 14-20.

After 32 clock cycles, the generator terminates and returns to its original state.

From the above it follows that the proposed generator really allows you to generate a complete orthogonal system of integrated signals in contrast

from famous. Therefore, the goal set in the invention, is fully implemented.

Claims (1)

The claims An orthogonal signal generator comprising a clock, a five-digit counter, four adders modulo two first groups, the first an integrator and four multipliers, the output of the clock generator being connected to the counter input, the i-ro and (i + 1) -ro bits of which are connected to the i-ro inputs of the adder modulo two of the first group (, 4), characterized in that, with In order to expand the functionality by forming a complete orthogonal system of integrated signals, it contains second to fourth integrators, two adders modulo two second groups, and fifth to eleventh multipliers, and (k1, ..., 3) the group of multipliers contains 2k -1 multipliers whose first inputs are soy ineny with outputs from the second the fourth integrator, the first to fourth integrator inputs are connected to the inputs of the respective adders modulo two of the first group, the outputs of the first and third bits of the counter are connected to the outputs of the first adder modulo two of the second group, the output of which is connected to the first input of the second adder modulo two second group, the second input of which is connected to the output of the second digit of the counter, the second inputs of the j-ro multiplier of the k-group (j 1,2) are connected to the outputs j-ro of the digit of the counter, respectively, the second inputs of the third multiplier the second and third groups are connected respectively with the outputs of the first adder modulo two of the first group and the output of the fourth bit of the counter, the output of the third bit of which is connected to the second input of the fourth multiplier of the third group, the second the inputs of the first, sixth and seventh multipliers of which are connected respectively to the output of the first adder modulo two of the first group, the outputs of the first and second adders modulo two of the second group, the outputs of the integrators and all multipliers are outputs of the generator. LL L. LL W AND. vVN / V w v V L L LL LL LL VV V V W V V lll lll  / V W vv w V AAvVVVV V -V% / - VAWA / VV VwVVv vwwwv ALLALLLL. / v V V V V VV / H / H UH / H N /  UCH / / V x / N / N / NX / Hh hh y x V V / o .; w