RU1772801C - Generator of discrete orthogonal signal system - Google Patents

Abstract

The invention relates to the field of automation and computer engineering and can be used in spectral analysis and communication devices to generate orthogonal signals. The purpose of the invention is to simplify a generator. The generator of a discrete orthogonal signal system contains a clock 1, a t-bit counter 2 (2-dimension of the signal system), t-1 cyclic 2-bit shift registers 3 (, gn-2 is the number of the cyclic shift register), 2t - 2 multipliers 4 of the first group, a signal level limiter 5, 2t-1 of multipliers 6 of the second group, the delay element 7. The input of the delay element to the generator allows halving the number of multipliers of the second group. 4 ill.

Description

The invention relates to the field of automation and computer engineering and can be used in communication spectral analysis devices to generate orthogonal signals.

An object of the invention is to simplify a generator.

Figure 1 presents the functional diagram of the generator (); figure 2 - system of Haar functions; Fig. 3-diagrams illustrating the formation of a pair of output signals Co (0) and C2 ©); figure 4 - output system of discrete orthogonal generator signals.

The generator of a discrete orthogonal signal system contains a clock 1, an m-bit binary counter 2, (2Sh is the dimension of the signal system), t-1 cyclic shift registers 3 (21 is the size of the 1st shift register, 1 1, t -1), 2t-2 multipliers 4 of the first group, a limiter 5 of the signal level, 2t-1 multipliers 6 of the second group, delay element 7.

The signals at the bit outputs of counter 2 are represented by levels +1, -1, which allows one to generate functions with the same values (Rademacher, Haar functions and generator output signals). In the initial state, all bits of the counter have a value of 1. In each of the registers 3, a code of the form 10 ... O (10 ... O, 010 ... 0.00 ... 01.10 ... O etc.), a one-bit shift is caused by a difference in any character at the control input of the register.

The signal level limiter 5 has a minimum restriction level of 0, i.e. passes only the positive part of the signals. Element 7 is characterized by a one-cycle delay (At).

The generator operates as follows.

When clock pulses are supplied from the generator 1 at the bit outputs of the counter 2, a system of m Rademacher signals Rk is generated (k 0, m-1 when numbering from the highest order). Signal Rk corresponds to k-e

(L

WITH

Yu

00

about

ZHEL

a subset of Haar functions 0 1-2k) formed by the kth subgroup of multipliers 4 (a multiplier is not required in the group, so

i1) Hi, (0

  ) 1, a subset is formed by multipliers

4.1,4.2, a subset; - multipliers mi 4.3-4.6. The sequence of values of the index I in the kth subset of Haar signals (exclusion) is generated by the kth shift register 3: the current position (1,2, ..., 2k) of the bit containing 1. Shift in the kth register (go to And 1) it is caused by both a positive and negative edge signal Rk-1, Haar signals of which subset are the result of multiplying the Rademacher signal Rk with the bit outputs of the k-ro shift register 3:

  Rk or Xk 0, depending on the value (1 or 0) of the corresponding register bit. The complete system of Haar functions is presented in FIG. 2.

The output system of discrete orthogonal signals 0, m-1, I - 1.2

is formed from Haar signals% kS by multiplying by a paraphase signal F1, Ф2: in subsets with values of k from O to t-2, multiplication by Ф2 is performed, in the subset, multiplication by F1. Phase F1 is generated by a signal level limiter 5, which isolates the positive portion of the signal Rm-i (low-order bit of counter 2). Phase F2 is delayed relative to F1 by one clock cycle and is generated by delay element 7. Multiplication is performed on multipliers 6.

Fig. 3 illustrates a signal generation process and Art.

a - output clock 1;

b - low-order output of counter 2 (signal Rrn-l);

c - output of the signal level limiter 5 (phase Ф i);

g - the output of the delay element 7 (phase F2);

d - high-order output of counter 2

(signal ROS% &);

e - output of the multiplier 4.3 (signal

1H

g, s - signals CC / C C2 (outputs of the corresponding multipliers 6).

The complete system of functions of the Ck® generator () is shown in FIG. 4.

Claims (1)

SUMMARY OF THE INVENTION A generator of a discrete orthogonal signal system comprising a clock generator, a gl-bit counter (2t is the dimension of a signal system), t-1 cyclic shift registers, 2t-2 multipliers of the first group, multipliers of the second group and a signal level limiter, the output being the clock generator is connected to the counting input of the m-bit counter, the 1st bit output of the t-bit counter (i 1, m-1 when numbering from the high-order side) is connected to the control input of the i-ro cyclic shift 0 shift register, (1 + 1) -th bit output of the t-bit counter is connected to the first inputs from the () -th to (2 | m-2) -th multipliers of the first group, the second inputs from (2 -1) -th by (2 | + 1-2) -th multipliers of the first group 5 are connected to the corresponding bit outputs of the 1st cyclic shift register (21 is the bit of the i-ro cyclic shift register), the first bit output of the m-bit counter is connected to the first 0 by the input of the first multiplier of the second group, output j-ro (,) multiplier first group connection the first input (J + 1) -ro multiplier of the second group, mth bit , the output of the m-bit counter is connected to 5 by the input of the signal level limiter, the output of the signal level limiter is connected to the second inputs from the (2m-1) th multipliers of the second group, the first bit output of the m-bit counter and the outputs of the multipliers of the first soil are outputs of the Haar signal system of the generator, the outputs of the multipliers of the second group are outputs of the discrete orthogonal signal system of the generator, which consists of the fact that, in order to simplify the generator, it contains a delay element, and the output of the signal level limiter is connected to the input of the element Derzhko, the delay element output is connected to vto0 rymi inputs of the first through the (2m 1) -th multipliers of the second group. Fig, 7 hz-j ju CZj-3 X (b) tr x fa) xffe)) xff9) T toe.3 n n r ,,,, Yu U u SU 16) P and - $ () -n f) f) P s (1} (c) P At IG tfV "