SU1675873A1 - Generator of sequences of codes - Google Patents

Abstract

The invention relates to automation and computing and can be used in spectral analysis devices and digital signal processing devices. The aim of the invention is to extend the functionality of the generator by generating sequences of D-codes. The generator contains counters 1. 2, elements And 3, adders 4, 7, 8 modulo two, ring registers 5 shift. Introducing the circular shift registers 5 and accumulators 8 into the generator allows to obtain all the D-code sequences by multiplying the zero sequence with the Walsh functions. 4 il.

Description

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The invention relates to automation and computing and can be used in spectral analysis devices and digital signal processing devices.

The purpose of the invention is to expand the functionality of the generator by generating D-code sequences.

FIG. 1 shows a functional diagram of the generator; 2 shows timing diagrams for forming the D-code sequence (J5; FIG. 3 shows the Walsh functions, and FIG. 4 shows the D-code sequences for 2k 8 cases.

The generator contains counters 1 and 2, elements 3, an adder 4 modulo two, circular four-bit registers 5 of the shift, a source 6 unit level, a group of adders 7 modulo two and an additional adder 8 modulo two.

The generator works as follows

The rule for building D-codes can be represented as

dik dpk Wi,

where do is the null D-code sequence;

Wi-i-Walsh function;

di - i- sequence P-cr /

2 - the number of sequences (i:

At the bit outputs of counter 1, a system of Rademacher functions is formed under the action of clock pulses. In counter 2, the current function number i is generated. Walsh. The number is changed at the end of each period of functions by the overflow signal of counter 1. The Walsh function Wj is formed on modulator 2 by multiplying the corresponding Rademacher functions (multiplication of sign functions is logically displayed by modulo two). The selection of the Rademacher functions in accordance with the number i is provided by the elements And 3.

The dok sequence is formed using four-bit ring shift registers 5 and modulo-2 adders 7. In each of the registers 5, the code 1000 is cyclically shifted, the shift frequency being set by the bit signals of counter 1 and halved when the register number is incremented by one. One of the inputs of the adder 7.1 modulo two is connected to the source 6 of a single level.

The multiplication according to (the D-code construction rule) is performed on the adder 8 modulo two, the inverse output of which

(EQUIVALENCE function) is the output of the generator.

The operation of the generator is illustrated by time diagrams.

Figure 2 shows the formation of a sequence of ds at the outputs of the circuit elements;

a) clock generator;

b) shift register 5.1;

0 c) source 6 unit level;

d) adder 7.1 modulo two;

e) the first discharge of counter 1;

f) shift register 5.2;

g) adder 7.2 modulo two;

5h) adder 4 modulo two in the period

forming the function Wai (5.0);

and) adder 8 modulo two in the period of the formation of the sequence ds. On fig.Z shows the Walsh function,

0 formed at the output of the adder 4 modulo two, ya figure 4 - d-code sequence for the case of 2k 8.

Claims (1)

Claim Generator Code Generator 5 containing two counters, elements And and a modulo-two adder, with the input of the first counter connected to the clock input of the generator, the overflow output of the first counter connected to the input of the second counter, the same-named bit outputs of the first and second counters connected to the corresponding input of the adder modulo two, characterized in that, for the purpose 5 extending the functionality of the generator by generating D-code sequences. it contains four-bit ring shift registers, a mod. two and a group of adders 0 an additional modulo two adder, the shift input of the first ring four-bit shift register is connected to the clock input of the generator, the i-th bit output of the counter (i 1, k 2, where k 5 is the first and second counters, 2k is the number of sequences D-codes) is connected to the shift input (i + 1} -th ring four-bit shift register, serial output of the j-th ring four 0-bit shift register, serial output of the j-ro ring four-bit shift register (j 171с- -1) connected to the first input ohm j-ro adder modulo two groups, the second input of the first adder modulo two groups connected to the source of a single level generator, the output of the i-ro modulo adder two groups connected to the second input of the (1 + 1) -th modulo adder two groups, an output modulo two and an output (k 1) of the modulo-2 adder, the two-inverse output of the additional sum-dinen with the corresponding inputs of the modulo-two is the output of the general modulo-2 adder. a ppppp R gp % GP GP yfJL R and. Ive 2 WaЈ (5.0} : diiValloA - Ji i t-i / al (1, B