RU1824631C - Device for generation of discrete orthogonal signals - Google Patents

Abstract

A device for generating discrete orthogonal signals belongs to the field of automation and computer engineering and can be used to create generator equipment for multichannel communication systems. The purpose of the invention is to increase the accuracy of the generated signals. The device contains a clock generator, an n-2-bit counter (2P the number of signals at the outputs of the device), a generator of the first-order Walsh function system, p-1 ring four-bit shift registers, and p-1 groups of signed multipliers with 2 signed multipliers in each group (where I- group). 4 ill. 1, n-1-pin number

Description

The invention relates to the field of automation and computer engineering and can be used to create generator equipment for multichannel communication systems.

An object of the invention is to improve the accuracy of simulated signals.

Figure 1 is a structural diagram of an apparatus for modeling discrete orthogonal signals; Fig. 2 is a timing diagram illustrating the process of generating a discrete orthogonal signal by the proposed device at the eighth output of the proposed device for case p-3; in Fig.3 - time diagrams of the Walsh functions formed at the outputs of the analogue; figure 4 - timing diagrams of the signals generated at the outputs of the proposed device.

A device for modeling discrete orthogonal signals contains

groups 1,2 ..., p-1 of the sign multipliers 7, four-bit circular registers 3.1-3, p-1 of the shift, which sets the generator 4, block 5 of the formation of Walsh functions of the first order (bit counter 6.

The device operates as follows (for the case).

In the initial state, all bits of the (n-2) -bit counter 6 are zeroed, and codes of the form 1000 are written in four-bit circular registers 3. In the order of its output, periodically repeated, a system of Walsh functions is formed:

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cl

with

oo

Yu

N WITH

The pulses from the output of the master oscillator 4 also arrive at the clock input of the ring four-bit register 3.1

shear, as a result of which it carries out a cyclic shift of a unit from one digit to another.

After four clock cycles, the signals will be generated at the outputs of block 5 of the formation of Walsh functions of the first order:

: -v- l

moreover, the first signal is fed to the inputs of signed multipliers 7.1 and 7.3, and the second signal is fed to the inputs of signed multipliers 7.2 and 7.4 of the first group.

The sign multipliers 7 are arranged in such a way that when they enter their sign inputs 0m, the outputs appearing at their outputs are unchanged, and when they enter their sign inputs G, their signals appear at the outputs their information inputs are inverted (in the technical literature, these elements are also called controlled inverters).

At the third clock cycle of the master oscillator 4 at the third bit output of the shift register 3.1, G appears, which arrives at the sign inputs of the sign multipliers 7.3 and 7.4 of the first group.

At the fourth clock cycle of the master oscillator 4, the third bit output of the shift register 3.1 appears 1, which is fed to the sign inputs of the sign multipliers 7.1 and 7.2 of the second group.

As a result, during the first four clock cycles of the clock 4 at the outputs of the first group of symbolic multipliers 7, a signal system will be formed:

4 4 + + - + i f + U - - -j

Since the registers 3 are four-bit circular, during the first eight clock cycles at the outputs of the first group of sign multipliers 7 a signal system will be formed:

J + 4 + - + ++.

i h- - + 4- h- f - 4+. - - +. ". - | ;

each of these signals being fed to the information inputs of two corresponding sign multipliers 7 of the second group.

During the first eight clock cycles of the master oscillator 4, pulses from its output go to the counter input of counter 6. and from the first bit output of the counter 6 to the clock input of shift register 3.2.

5

8, the result in the fifth and sixth clock cycles at the third bit output of the shift register 3.2 is the 1st, which goes to the sign inputs of the sign multipliers 7.5, 7.6. 7.7 and 7.8 of the second group.

At the seventh and eighth clock cycles, at the fourth bit output of the shift register 3.2, 1 appears, which arrives at the sign inputs of the sign multipliers 7.1, 7.2, 7.3 and 7.4 of the second group.

Thus, during the first eight clock cycles, the discrete orthogonal signals V (l, c) will be modeled at the outputs of the symbolic multipliers 7 of the second group:

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5

0

5

0

5

5, the operation of the device is subsequently carried out as described above. On Fig, 2 shows a timing diagram illustrating the process of forming the proposed device

0 discrete signal V (7.c) (for case). The diagrams show the temporary state:

a) the output of the master oscillator 4;

b) the second output of the first order Walsh generation unit 5;

c) the third bit output of the annular four-bit shift register 3.1;

d) the output of the significant multiplier 7.4 of the first group;

e) the output of the first bit of counter 6:

e) the third bit output of the circular four-bit register 3.2 shift:

g) the output of the sign multiplier 7.8 of the shift of the second group.

Since the first order Walsh function generating unit 5 is much simpler than the Walsh function generating unit used in the prototype, the first order Walsh function generating unit 5 may contain, for example, a single signal source 1 and provide a direct connection of the meander output of the master oscillator 4 with inputs signed multipliers 7.2 and 7.4. then in the proposed device there is no source of instrumental error in the form of a unit for generating Walsh functions. consisting of a counter and p-1 groups of multipliers present in the prototype. That is, the proposed device for modeling discrete orthogonal signals is completely free from the disadvantage that the accuracy of the modeled signals is reduced due to the fact that a different number of multipliers inherent in the prototype participate in the formation of a function.

In the proposed device, when modeling each discrete signal, the same number of signed multipliers is used 7. For a system of discrete orthogonal signals of dimension n, the number of signed multipliers 7. involved in the simulation of each discrete signal is n-1.

Using the invention, it is possible to create generator equipment for multichannel communication systems, which improves the accuracy of the generated signals.

FORMULA AND SECTION

A device for generating discrete orthogonal signals containing a master oscillator, a unit for generating Walsh functions of the first order, a (p-2) -bit counter (2P is the number of signals at the outputs of the device), p-1 ring four-bit shift registers, and the first a group of signed multipliers, the output of the master oscillator being connected to the clock input of the Walsh function generation unit of the first order, to the counter input of the counter and the clock input of the first ring four-bit shift register, the jth bit output of the counter (,

p-2 - bit numbering from the low-order side) is connected to the clock input of the (J + 1) -ro ring four-bit shift register, characterized in that, in order to increase the accuracy of the generated signals, p-2 groups of signed multipliers, and in each group of 2 signed multipliers (where, n-1), the first output of the first-order Walsh function generation unit is connected to the information inputs of the first and third significant multipliers of the first group, the second output of the first-order Walsh function formation unit info to the input inputs of the second and fourth signed multipliers of the first group, the third bit output of the first annular four-digit shift register is connected to the sign inputs of the third and fourth signed multipliers of the first group, the fourth bit output of the first annular four-digit shift is connected to the sign inputs of the first and second signed multipliers of the first group, the output of the k-ro sign multiplier (where k is the iT jI-ii group is connected to the information inputs of the k-ro and () -ro sign multipliers of the (1 + 1) th group, the third p the first output of the 1st annular four-digit shift register (where, p-1) is connected to the sign inputs from (2 +1) to the 2nd significant multipliers of the 1st group, the fourth bit output of the 1st annular four-digit of the first shift register is connected to the sign inputs from the first to the second sign multipliers of the 1st group, the outputs of the sign multipliers of the (n-1) th group are the outputs of the device.

Fig