RU2620988C1 - Jeffy code sequences generator - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: Jeffy code sequence generator contains the clock oscillator (1), block (2) forming the Walsh functions, impulses shaper (3), trigger (4), the first key (5), the second key (6), adder (7), 2ⁿ multipliers (8) of the first group, 2ⁿ multipliers (9) of the second group, 2^n-1 -bit cyclic shift register (10), driven inverter (11), frequency divider (12), four cyclic shift register (13), the first additional key (14), the second additional key (15), the third additional key (16), the fourth additional key (17) and the four-input summator (18).

EFFECT: functionality extension by forming the sequences of the Jeffy code.

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Description

The invention relates to automation and computer technology and can be used to create generator equipment for multi-channel communication systems, including those using LTE technology, to build information and information and communication systems for various purposes.

A well-known generator of discrete orthogonal functions, containing a clock generator, a unit for generating Walsh functions, a frequency divider, switches and signed multipliers (see copyright certificate for the invention No. 1686429, class G06F 1/02, published in bulletin No. 39 dated 10.23.1991 )

The disadvantages of the known generator of discrete orthogonal functions are limited functionality, since it generates the signals of the sequences L (i, θ), but does not provide the generation of Jeffey code sequences.

A device is known for generating a system of discrete orthogonal functions, comprising a clock, a unit for generating Walsh functions, a unit for generating a second-order Hadamard function system, multipliers, a switch, a counter, four-digit shift registers, an adder modulo two, signed multipliers (see copyright certificate for the invention No. 1689940, class G06F 1/02, published in bulletin No. 41 dated November 7, 1991).

The disadvantages of the known device for forming a system of discrete orthogonal functions are limited functionality, since it forms a system of D-code sequences, but does not provide the generation of Jeffy code sequences.

Closest to the technical nature of the present invention is a discrete orthogonal signal generator that generates a modified Reed-Muller code sequence containing a clock, a Walsh function generation unit, a pulse shaper, a trigger, two keys, an adder, 2 ⁿ multipliers of the first group (2 ⁿ - the number of outputs of the unit for generating Walsh functions), 2 ⁿ multipliers of the second group, 2 ⁿ inverters, 2 ^n-1 - bit cyclic shift register and controlled inverter, and the output of the clock generator it is connected to the clock input of the Walsh function generation unit, the output of the pulse former is connected to the counting input of the trigger, the inverse and direct outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of the first and second keys are connected to the inputs of the adder, the outputs of the Walsh function formation unit are connected to respective second inputs of the multipliers of the first group, output the second Walsh function generation unit Walsh functions connected with the input pulse shaper outputs 2 ^n-1 -th and the (2 ⁿ -1) -th function ii Walsh forming unit Walsh functions are respectively connected to data inputs of the first and second keys, the adder output being connected to an information input of a controlled inverter, the control input of which is connected to the output of the most significant bit 2 ^n-1 cyclic -bit shift register, a clock input connected to the output of the clock generator, the output of the controlled inverter is connected to the first inputs of the multipliers of the first group and the multipliers of the second group, the outputs of the unit for generating Walsh functions through inverters yucheny to the second inputs of respective multipliers of the second group, the outputs of the multipliers of the first and second groups are of the generator output (see. patent for invention No. 2022332, class G06F 1/025, published in Bulletin No. 20 of 10/30/1994).

However, the well-known discrete orthogonal signal generator generating sequences of the modified Reed-Muller code has limited functionality since it cannot generate Jeffy code sequences.

The aim of the invention is to expand the functionality of the generator, which consists in the formation of sequences of Jeffery code.

Geoffy code sequences with orthogonal properties are widely used to create generator equipment for multichannel communication systems, to build information and infocommunication systems for various purposes (see page 140, Pestryakov VB Noise-like signals in information transmission systems. - M .: Soviet Radio, 1973, p. 424). On page 140 of the indicated source (first paragraph from the bottom) it is noted that the mutating (i.e. generating) Jeffy sequence when multiplied by the Reed-Muller sequence (or Walsh function) gives an ensemble of Jeffy sequences (Jeffy code sequence system).

The mutating (i.e. producing) Jeffy sequence in this source is indicated as follows:

(see the first paragraph from below on page 140 of the source - Pestryakov VB Noise-like signals in information transmission systems. - M.: Soviet Radio, 1973, p. 424).

The sequences of Jeffy's code are mathematically constructed as follows: each function of the original system of Walsh functions is multiplied element-wise by the generating sequence of the Jeffy code, having the form

In this case, the Walsh functions in the original system of Walsh functions must be ordered by increasing the number of alternating signs in each function, that is, ordered by Walsh (Trakhtman AM, Trakhtman V.A. Fundamentals of the theory of discrete signals at finite intervals. - M.: Soviet radio, 1975 , p. 47, relation (2.4)).

In this case, the Walsh function system has the form:

The result of multiplying each function of the original system of Walsh functions (2) by the generating sequence (1) of the Jeffy code, the system of sequences of the Jeffy code is orthogonal (see page 140, Pestryakov VB Noise-like signals in information transfer systems. - M .: Soviet radio, 1973, p. 424) and has the following form:

This goal is achieved by the fact that in the well-known generator of discrete orthogonal signals containing a clock, a Walsh function generation unit, a pulse shaper, a trigger, two keys, an adder, 2 ⁿ multipliers of the first group (2 ⁿ is the number of outputs of the Walsh function formation unit), 2 ⁿ multipliers of the second group, 2 ^n-1 - bit cyclic shift register and controlled by an inverter, wherein the clock output is connected to the clock input of Walsh functions forming unit, pulse shaper connected to the output countable the trigger, the inverse and direct outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of the first and second keys are connected to the inputs of the adder, the outputs of the Walsh function generation unit are connected to the second inputs of the corresponding multipliers of the first group, the second output of the Walsh function formation unit is connected to pulse shaper input, the adder output is connected to the information input of the controlled inverter, the control input of which is connected to the output of the senior bit 2 ^n-1 - bit about a cyclic shift register, the clock input of which is connected to the output of the clock generator, the output of the controlled inverter is connected to the first inputs of the multipliers of the first group, a frequency divider, a cyclic four-digit shift register, four additional keys and a four-input adder are introduced, and the outputs of the Walsh function generation unit are connected to the second inputs of respective multipliers of the second group (2 ⁿ -4) th output and (2 ^n-1 -2) -th unit output forming Walsh functions considering the fact that Walsh function on the outputs of odds block Walsh functions are ordered by increasing number of alternating signs in each function, connected respectively to the information inputs of the first and second keys, the output of the clock generator is connected to the input of the frequency divider, the output of which is connected to the clock input of the cyclic four-digit shift register, the outputs of the discharges of which are connected to the control inputs of the corresponding additional keys, yield (2 ⁿ -1) -th multiplier of the first group is connected to the first data input of an additional key, the output ^{(n-2 1} -3) -th mind ozhitelya first group is connected to the data input of a second additional key, the output (2 ^n-1 -2) th multiplier of the first group is connected to the data input of the third additional key -th multiplier output 2 of the first group is connected to the data input of the fourth additional key, additional outputs keys are connected to the inputs of the four-input adder, the output of which is connected to the first inputs of the multipliers of the second group, the outputs of the multipliers of the second group are the outputs of the generator, on which the last Jeffery Code.

In FIG. 1 is a structural diagram of a Jeffey code sequence generator; FIG. 2 is a timing diagram illustrating the process of generating a signal S (10, θ) at the output of the eleventh multiplier 8 of the first group for case 2 ⁿ = 16, in FIG. 3 is a timing diagram illustrating the process of generating a sequence of Jeffery code J (10, θ) at the output of the eleventh multiplier 9 of the second group for case 2 ⁿ = 16, in FIG. 4 is a view of the Walsh functions at the outputs of the Walsh function generation unit 2, FIG. 5 is a view of Reed-Muller code sequences starting with a positive element generated at the outputs of the respective multipliers 8 of the first group, FIG. 6 is a view of Jeffy code sequences generated at the outputs of the respective multipliers 9 of the second group.

Jeffy's code sequence generator contains a clock 1, a Walsh function generation unit 2, a pulse shaper 3, a trigger 4, a first key 5, a second key 6, an adder 7, 2 ⁿ multipliers 8 of the first group, 2 ⁿ multipliers 9 of the second group, 2 ^{n- 1} - bit cyclic shift register 10, controlled inverter 11, frequency divider 12, four-bit cyclic shift register 13, first additional key 14, second additional key 15, third additional key 16, fourth additional key 17 and four-input adder 18.

Jeffy's code sequence generator works as follows.

Before starting the Jeffrey code sequence generator, the unit is written to the (2 ^n-1 -3) th digit of the cyclic shift register 10, and the unit is written to the first bit of the four-bit cyclic shift register 13.

Trigger 4 is in the initial single state. Potentials from the inverse and direct outputs of trigger 4 are supplied to the control inputs of keys 5 and 6, respectively. Thus, the key 6 is open, and the key 5 is closed. Under the influence of pulses from the output of the clock generator 1 (Fig. 2, a) at the outputs of block 2 Walsh functions are formed. The Wal function (5, θ) with the (2 ^n-1 -2) -th output (Fig. 2, c) of the Walsh function generation block (the functions are ordered at the outputs of block 2 by increasing the number of alternating signs in each function, that is, they are ordered by Walsh ) through the public key 6 enters the input of the adder 7 (Fig. 2, d), and from its output to the information input of the controlled inverter 11.

At the moment of changing the sign, the Walsh function Wal (1, θ) generated at the second output of block 2 (Fig. 2, b) triggers the pulse shaper 3. The pulses from its output change the state of trigger 4, and therefore the state of keys 5 and 6. As a result, the second key 6 is closed, and the first key 5 is open, and the Walsh function Wal (11, θ) with (2 ⁿ - 4) -th output (Fig. 2, d) of block 2 through the public key 5 is fed to the input of the adder 7 (Fig. 2, e), and from its output to the information input of the controlled inverter 11.

On the third clock cycle of the generator, at the output 2 of the ^n-1 -bit cyclic shift register 10, a unit is formed that was recorded in the (2 ^n-1 -3) -th bit of the cyclic shift register 10 (Fig. 2, h). This unit arrives at the control input of the controlled inverter 11, as a result of which the third element of the signal generated at the output of the adder 7 (Fig. 2, g) and fed to the information input of the controlled inverter 11 is inverted (Fig. 2, and).

At the eleventh cycle of the generator, at the output 2 of the ^n-1 -bit cyclic shift register 10, a unit is formed that was recorded in the (2 ^n-1 -3) -th bit of the cyclic shift register 10 (Fig. 2, h). This unit arrives at the control input of the controlled inverter 11, as a result of which the eleventh element of the signal generated at the output of the adder 7 (Fig. 2, g) and fed to the information input of the controlled inverter 11 is inverted (Fig. 2, and).

The signal generated at the output of the controlled inverter 11 is multiplied in the multipliers 8 of the first group by the Walsh function. As a result of this, at the outputs of the multipliers 8 a signal system S (i, θ) is formed, which is a sequence of Reed-Mueller code starting with a positive element. For example, when the signal from the output of the controlled inverter 11 (Fig. 2, and) is multiplied by the Walsh function Wal (10, θ) (Fig. 2, y), a signal is generated at the output of the corresponding multiplier 8 of the first group, which is a sequence of Reed-Muller code S (10, θ) starting with a positive element.

. То есть первый импульс на выходе сформируется через

длительности функций Уолша, второй импульс - через

длительности функций Уолша, третий импульс - через

длительности функций Уолша, четвертый импульс - по завершении длительности функций Уолша (фиг. 3, б). В результате единица, записанная в первом разряде четырехразрядного циклического регистра 13 сдвига, последовательно переместится из первого во второй разряд, потом из второго в третий, потом из третьего в четвертый, а затем из четвертого в первый разряд, поскольку регистр 13 сдвига является циклическим.The pulses from the output of the clock generator 1 (Fig. 3, a) are also received at the input of the frequency divider 12, having a division ratio equal to

. That is, the first pulse at the output is formed through

duration of Walsh functions, the second impulse - through

duration of Walsh functions, the third impulse - through

duration of Walsh functions, the fourth impulse - at the end of the duration of Walsh functions (Fig. 3, b). As a result, the unit recorded in the first bit of the four-bit cyclic shift register 13 will sequentially move from the first to the second bit, then from the second to the third, then from the third to the fourth, and then from the fourth to the first bit, since the shift register 13 is cyclic.

During the first quarter of the duration of the formation of the Walsh functions, the unit is in the first category of the four-digit cyclic shift register 13. In this case, the first additional key 14 is in the open state (Fig. 3, d), and the remaining additional keys are in the closed state. As a result, the first quarter of the signal S (2 ^n-1 -2, θ), generated at the output of the (2 ^n-1 -1) -th multiplier of the first group, is received at the first information input of the four-input adder 18. In the case 2 ⁿ = 16, this will be the signal S (6, θ) (Fig. 3, c).

During the second quarter of the duration of the formation of the Walsh functions, the unit is in the second category of the four-digit cyclic shift register 13. In this case, the second additional key 15 is in the open state (Fig. 3, e), and the remaining additional keys are in the closed state. As a result, the second quarter of the signal S (2 ^n-1 -4, θ), generated at the output of the (2 ^n-1 -3) -th multiplier of the first group, is received at the second information input of the four-input adder 18. In the case 2 ⁿ = 16, this will be the signal S (4, θ) (Fig. 3, d).

During the third quarter of the duration of the formation of the Walsh functions, the unit is in the third category of the four-digit cyclic shift register 13. In this case, the third additional key 16 is in the open state (Fig. 3, h), and the remaining additional keys are in the closed state. As a result, the third quarter of the signal S (2 ^n-1 -3, θ) generated at the output of the (2 ^n-1 -2) -th multiplier of the first group will arrive at the third information input of the four-input adder 18. In the case 2 ⁿ = 16, this will be the signal S (5, θ) (Fig. 3, g).

During the fourth quarter of the duration of the formation of the Walsh functions, the unit is in the fourth category of the four-bit cyclic shift register 13. In this case, the fourth additional key 17 is in the open state (Fig. 3, d), and the remaining additional keys are in the closed state. As a result, the fourth information signal of the four-input adder 18 receives the fourth quarter of the signal S (1, θ) generated at the output of the 2nd multiplier of the first group. In the case 2 ⁿ = 16 it will be a signal S (1, θ) (Fig. 3, and).

The signal generated at the output of the four-input adder 18 is a generating sequence J (0, θ) of the Jeffy code. For example, for case 2 ⁿ = 16, the generating sequence J (0, θ) of the Jeffery code (Fig. 3, k) has the form:

To obtain, for example, the sequence of the Jeffery code J (10, θ) (Fig. 3, m), the Walsh function Wal (10, θ) (Fig. 3, l) is multiplied elementwise by the generating sequence J (0, θ) (Fig. 3, k) in the corresponding multiplier 9 of the second group.

In FIG. 2 are diagrams illustrating, as an example, the process of generating in the proposed signal generator S (10, θ) at the output of the corresponding multiplier 8 of the first group.

In the diagrams of FIG. 2 indicates a temporary state:

a) the output of the clock generator 1;

b) the second output of block 2 of the formation of Walsh functions, on which the function Wal (1, θ) is generated;

c) the sixth output of the Walsh function generation unit 2, on which the function Wal (5, θ) is generated;

d) the twelfth output of block 2 of the formation of Walsh functions, on which the function Wal (11, θ) is generated;

d) key output 6;

e) key output 5;

g) the output of the two-input adder 7;

h) the output of the senior bit 2 ^n-1 - bit cyclic shift register 10;

i) the output of the controlled inverter 11;

j) the eleventh output of block 2 of the formation of Walsh functions, on which the function Wal (10, θ) is generated;

j) the output of the eleventh multiplier 8 of the first group, on which the function S (10, θ) is formed.

In FIG. Figure 3 shows diagrams illustrating, by way of example, the process of generating the Jeffrey code sequence J (10, θ) in the proposed code generator.

In the diagrams of FIG. 3 indicates a temporary state:

a) the output of the clock generator 1;

b) the output of the frequency divider 12;

c) the output of the seventh multiplier 8 of the first group, on which the signal S (6, θ) is generated;

d) the output of the first additional key 14, on which the first quarter of the signal S (6, θ) is generated;

d) the output of the fifth multiplier 8 of the first group, on which the signal S (4, θ) is generated;

e) the output of the second additional key 15, on which the second quarter of the signal S (4, θ) is generated;

g) the output of the sixth multiplier 8 of the first group, on which the signal S (5, θ) is generated;

h) the output of the third additional key 16, on which the third quarter of the signal S (5, θ) is generated;

i) the output of the second multiplier 8 of the first group, on which the signal S (1, θ) is generated;

j) the output of the fourth additional key 17, which forms the fourth quarter of the signal S (l, θ);

j) the output of the four-input adder 18, on which a signal is generated, which is a generating sequence J (0, θ) of the Jeffy code;

k) the eleventh output of block 2 of the formation of Walsh functions, on which the function Wal (10, θ) is generated;

m) the output of the eleventh multiplier 9 of the second group, on which the Jeffy code sequence J (10, θ) is formed.

Thus, the proposed Jeffey code sequence generator has advanced functionality, which consists in the formation of Jeffy code sequences, and can be used to create generator equipment for multi-channel communication systems, including those using LTE technology, to build information and information and communication systems for various purposes.

Claims (1)

Jeffy's code sequence generator, containing a clock, Walsh function generation unit, pulse generator, trigger, two keys, adder, 2 ⁿ multipliers of the first group (2 ⁿ is the number of outputs of the Walsh function generation unit), 2 ⁿ multipliers of the second group, 2 ^{n- 1} - bit cyclic shift register and controlled by an inverter, the output of the clock generator is connected to the clock input of block formation of the Walsh functions, the pulse shaper output is connected to the count input of flip-flop inverted and direct outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of the first and second keys are connected to the inputs of the adder, the outputs of the Walsh function generation unit are connected to the second inputs of the corresponding multipliers of the first group, the second output of the Walsh function formation unit is connected to the input of the pulse former, the output of the adder is connected to managed data input inverter, the control input of which is connected to the output of the most significant bit 2 ^n-1 - bit cyclic shift register, the clock input of which о is connected to the output of the clock generator, the output of the controlled inverter is connected to the first inputs of the multipliers of the first group, characterized in that in order to expand the functionality of the generator, which consist in the formation of Jeffie code sequences, a frequency divider, a cyclic four-digit shift register, four additional keys are introduced into it and a four-input adder, and the outputs of the Walsh function generation unit are connected to the second inputs of the corresponding multipliers of the second group, (2 ⁿ -4) -th output and (2 ^{The n-1} -2) -th output of the Walsh function generation unit is connected respectively to the information inputs of the first and second keys, the output of the clock generator is connected to the input of the frequency divider, the output of which is connected to the clock input of the cyclic four-digit shift register, the discharge outputs of which are connected to the control inputs corresponding additional keys, the output of the (2 ^n-1 -1) -th multiplier of the first group is connected to the information input of the first additional key, the output of the (2 ^n-1 -3) -th multiplier of the first group is connected to inform To the input of the second additional key, the output of the (2 ^n-1 -2) -th multiplier of the first group is connected to the information input of the third additional key, the output of the 2nd multiplier of the first group is connected to the information input of the fourth additional key, the outputs of the additional keys are connected to the inputs of the four-input the adder, the output of which is connected to the first inputs of the multipliers of the second group, the outputs of the multipliers of the second group are the outputs of the generator, on which the Jeffy code sequences are formed.

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