RU2668742C1 - Generator of sequences of stiffler code - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to automation and computer technology and can be used to create generator equipment of multi-channel communication systems. Stiffler code sequence generator contains clock generator (1), Walsh function generation unit (2), pulse driver (3), trigger (4), first switch (5), second switch (6), adder (7), 2multipliers (8) of the first group, 2multipliers (9) of the second group, 2– cyclic shift register (10), controlled inverter (11), frequency divider (12), four-bit cyclic shift register (13), first additional key (14), second additional key (15), third additional key (16), fourth additional key (17), four-input adder (18) and delay element (19).EFFECT: technical result is to expand the functionality by forming sequences of the Stiffler code.1 cl, 6 dwg

Description

The invention relates to automation and computer technology and can be used to create generator equipment for multi-channel communication systems, including those using LTE technology, to build information and information and communication systems for various purposes.

A well-known generator of discrete orthogonal functions, containing a clock generator, a unit for generating Walsh functions, a frequency divider, switches and signed multipliers (see copyright certificate for the invention No. 1686429, class G06F 1/02, published in bulletin No. 39 dated 10.23.1991 )

A disadvantage of the known generator of discrete orthogonal functions is limited functionality, since it generates L (i, θ) sequence signals, but does not provide Stiffler code sequence generation.

A device is known for generating a system of discrete orthogonal functions, comprising a clock, a unit for generating Walsh functions, a unit for generating a system of second-order Hadamard functions, multipliers, a switch, a counter, four-digit shift registers, an adder modulo two, signed multipliers (see copyright certificate for the invention No. 1689940, class G06F 1/02, published in bulletin No. 41 dated November 7, 1991).

A disadvantage of the known device for forming a system of discrete orthogonal functions is limited functionality, since it forms a D-code sequence system, but does not generate Stiffler code sequences.

A known generator of discrete orthogonal signals that generates sequences of a modified Reed-Muller code containing a clock generator, a Walsh function generation unit, a pulse shaper, a trigger, two keys, an adder, 2 ⁿ multipliers of the first group (2 ⁿ is the number of outputs of the Walsh function generation unit), 2 ⁿ multipliers of the second group, 2 ⁿ inverters, 2 ^n-1 - bit cyclic shift register and controlled inverter (see patent for the invention No. 2022332, CL G06F 1/025, published in bulletin No. 20 dated 10.30.1994) .

However, the well-known discrete orthogonal signal generator generating sequences of the modified Reed-Muller code has limited functionality since it cannot generate the Stiffler code sequences.

The closest in technical essence to the present invention is a discrete orthogonal signal generator that generates Jeffey code sequences, containing a clock generator, a Walsh function generator, a pulse shaper, a trigger, two keys, an adder, 2 ⁿ multipliers of the first group (2 ⁿ is the number of outputs of the block forming Walsh functions), ⁿ 2 of the second group of multipliers, 2 ^n-1 - bit cyclic shift register and controlled inverter, a frequency divider, a cyclic four-bit shift register, four additional dome a key and a four-input adder, the output of the clock generator being connected to the clock input of the Walsh function generation unit, the output of the pulse shaper connected to the counting input of the trigger, the inverse and direct outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of the first and second keys are connected to the inputs of the adder, the outputs of the unit for generating Walsh functions are connected to the second inputs of the corresponding multipliers of the first group, the second output of the unit for generating Walsh functions with is single with the input of the pulse shaper, the adder output is connected to the information input of the controlled inverter, the control input of which is connected to the output of the highest bit 2 ^n-1 - bit cyclic shift register, the clock input of which is connected to the output of the clock generator, the output of the controlled inverter is connected to the first inputs of the multipliers of the first group, the outputs of the Walsh function formation unit are connected to the second inputs of the corresponding multipliers of the second group, (2 ⁿ -4) -th output and (2 ^n-1 -2) -th output of the Wo function formation unit Lhs are connected respectively to the information inputs of the first and second keys, the output of the clock generator is connected to the input of the frequency divider, the output of which is connected to the clock input of the cyclic four-digit shift register, the outputs of the bits of which are connected to the control inputs of the corresponding additional keys, output (2 ^n-1 -1 ) of the first multiplier of the first group is connected to the information input of the first additional key, the output of the (2 ^n-1 -3) of the first multiplier of the first group is connected to the information input of the second additional to In this case, the output of the (2 ^n-1 -2) -th multiplier of the first group is connected to the information input of the third additional key, the output of the 2nd multiplier of the first group is connected to the information input of the fourth additional key, the outputs of the additional keys are connected to the inputs of the four-input adder, the output of which connected to the first inputs of the multipliers of the second group, the outputs of the multipliers of the second group are the outputs of the generator on which the sequences of the Jeffy code are formed (see patent for invention No. 2620988, class G06F 1/02, published in Bulletin No. 16 dated 05/30/2017).

However, the well-known discrete orthogonal signal generator that generates Jeffey code sequences has limited functionality since it cannot generate Stiffler code sequences.

The aim of the invention is to expand the functionality of the generator, which consists in the formation of stiffler code sequences.

Stiffler code sequences with orthogonal properties are widely used to create generator equipment for multichannel communication systems, to build information and infocommunication systems for various purposes (see page 141, Pestryakov VB Noise-like signals in information transmission systems. - M .: Soviet Radio, 1973, p. 424). On page 141 of the indicated source (third paragraph from the bottom) it is noted that the mutating (i.e. producing) Stiffler sequence when multiplied by the Reed-Muller sequence (or Walsh function) gives an ensemble of Stiffler sequences (system of Stiffler code sequences).

Moreover, a comparison of the autocorrelation functions (FAK) and the cross-correlation functions (CVF) of Stiffler sequences and Digilock sequences, which include, among other things, Jeffy code sequences, shows that Stiffler sequences have better correlation properties (see the first paragraph below on the page 141 sources - Pestryakov VB Noise-like signals in information transmission systems. - M.: Soviet Radio, 1973, p. 424).

The mutating (i.e. producing) Stiffler sequence in this source is indicated as follows:

1101110000101000

(see the third paragraph from the bottom on page 141 of the source - Pestryakov VB Noise-like signals in information transmission systems. - M .: Soviet Radio, 1973, p. 424).

The Stiffler code sequences are mathematically constructed as follows: each function of the original system of Walsh functions is multiplied elementwise by a generating sequence of the Stiffler code of the form

In this case, the Walsh functions in the original system of Walsh functions must be ordered by increasing the number of alternating signs in each function, that is, ordered by Walsh (Trakhtman AM, Trakhtman V.A. Fundamentals of the theory of discrete signals at finite intervals. - M.: Soviet radio, 1975 , p. 47, relation (2.4)).

In this case, the Walsh function system has the form:

The result of multiplying each function of the original system of Walsh functions (2) by the generating sequence (1) of the Stiffler code, the system of sequences of the Stiffler code is orthogonal (see page 141, Pestryakov VB Noise-like signals in information transfer systems. - M .: Soviet radio, 1973, p. 424) and has the following form:

This goal is achieved by the fact that in the well-known generator of discrete orthogonal signals containing a clock, a Walsh function generation unit, a pulse shaper, a trigger, two keys, an adder, 2 ⁿ multipliers of the first group (2 ⁿ is the number of outputs of the Walsh function formation unit), 2 ⁿ multipliers of the second group, 2 ^n-1 - bit cyclic shift register and controlled inverter, frequency divider, cyclic four-bit shift register, four additional keys and four-input adder, and the clock output the ator is connected to the clock input of the Walsh function generation unit, the output of the pulse former is connected to the counting input of the trigger, the inverse and direct outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of the first and second keys are connected to the inputs of the adder, the outputs of the Walsh function formation unit are connected to the second inputs of the respective multipliers of the first group, the second output of the Walsh function generation unit is connected to the input of the pulse shaper, the adder output is connected to the info the controlled input of the controlled inverter, the control input of which is connected to the output of the high order 2 ^n-1 - bit cyclic shift register, the clock input of which is connected to the output of the clock generator, the output of the controlled inverter is connected to the first inputs of the multipliers of the first group, the outputs of the Walsh function generation unit are connected to the second inputs of the respective multipliers of the second group, the (2 ⁿ -4) -th output and (2 ^n-1 -2) -th output of the Walsh function generation unit are connected respectively to the information inputs of the first and second keys, the output of the clock generator is connected to the input of the frequency divider, the output of which is connected to the clock input of the cyclic four-digit shift register, the outputs of the bits of which are connected to the control inputs of the corresponding additional keys, the outputs of the additional keys are connected to the inputs of the four-input adder, the output of which is connected to the first inputs of the second multipliers group introduced delay element, said output (2 ^n-1 -2) th multiplier of the first group is connected to the data input of the first additional Cl Cha, yield (2 ^n-1 -4) th multiplier of the first group is connected to the data input of a second additional key, the output (2 ^n-1 +2) th multiplier of the first group is connected to the data input of the third additional key output (2 ^{n -1} +1) -th multiplier of the first group is connected to the input of the delay element, the output of the delay element is connected to the information input of the fourth additional key, the outputs of the multipliers of the second group are the outputs of the discrete orthogonal signal generator, on which stiffle code sequences are formed yep.

In FIG. 1 is a structural diagram of a Stiffler code sequence generator; FIG. 2 is a timing diagram illustrating the process of generating a signal S (10, θ) at the output of the eleventh multiplier 8 of the first group for case 2 ⁿ = 16, in FIG. 3 is a timing diagram illustrating the process of generating the Stiffler code sequence Stif (10, θ) at the output of the eleventh multiplier 9 of the second group for case 2 ⁿ = 16, in FIG. 4 is a view of the Walsh functions at the outputs of the Walsh function generation unit 2, FIG. 5 is a view of Reed-Muller code sequences starting with a positive element generated at the outputs of the respective multipliers 8 of the first group, FIG. 6 is a view of the stiffler code sequences generated at the outputs of the respective multipliers 9 of the second group.

The Stiffler code sequence generator comprises a clock 1, a Walsh function generation unit 2, a pulse shaper 3, a trigger 4, a first key 5, a second key 6, an adder 7, 2 ⁿ multipliers 8 of the first group, 2 ⁿ multipliers 9 of the second group, 2 ^{n- 1} - bit cyclic shift register 10, controlled inverter 11, frequency divider 12, four-bit cyclic shift register 13, first additional key 14, second additional key 15, third additional key 16, fourth additional key 17, four-input adder 18 and element 1 9 delays.

The Stiffler code sequence generator works as follows.

Before the Stiffler code sequence generator starts, the unit is recorded in the (2 ^n-1 -3) -th bit of the cyclic shift register 10, and the unit is recorded in the first bit of the four-bit cyclic shift register 13.

Trigger 4 is in the initial single state. Potentials from the inverse and direct outputs of trigger 4 are supplied to the control inputs of keys 5 and 6, respectively. Thus, the key 6 is open, and the key 5 is closed. Under the influence of pulses from the output of the clock generator 1 (Fig. 2, a) at the outputs of block 2 Walsh functions are formed. The Wal function (5, θ) with the (2 ^n-1 -2) -th output (Fig. 2, c) of the Walsh function generation block (the functions are ordered at the outputs of block 2 by increasing the number of alternating signs in each function, that is, they are ordered by Walsh ) through the public key 6 enters the input of the adder 7 (Fig. 2, d), and from its output to the information input of the controlled inverter 11.

At the moment of changing the sign, the Walsh function Wal (1, θ) generated at the second output of block 2 (Fig. 2, b) triggers the pulse shaper 3. The pulses from its output change the state of trigger 4, and therefore the state of keys 5 and 6. As a result, the second key 6 is closed, and the first key 5 is open, and the Walsh function is Wal (11, θ) with (2 ⁿ -4) -th output (Fig. 2, d) of block 2 through the public key 5 is fed to the input of the adder 7 (Fig. 2, e), and from its output to the information input of a controlled inverter 11.

On the third clock cycle of the generator, at the output 2 of the ^n-1 -bit cyclic shift register 10, a unit is formed that was recorded in the (2 ^n-1 -3) -th bit of the cyclic shift register 10 (Fig. 2, h). This unit arrives at the control input of the controlled inverter 11, as a result of which the third element of the signal generated at the output of the adder 7 (Fig. 2, g) and fed to the information input of the controlled inverter 11 is inverted (Fig. 2, and).

At the eleventh cycle of the generator, at the output 2 of the ^n-1 -bit cyclic shift register 10, a unit is formed that was recorded in the (2 ^n-1 -3) -th bit of the cyclic shift register 10 (Fig. 2, h). This unit arrives at the control input of the controlled inverter 11, as a result of which the eleventh element of the signal generated at the output of the adder 7 (Fig. 2, g) and fed to the information input of the controlled inverter 11 is inverted (Fig. 2, and).

The signal generated at the output of the controlled inverter 11 is multiplied in the multipliers 8 of the first group by the Walsh function. As a result of this, at the outputs of the multipliers 8 a signal system S (i, θ) is formed, which is a sequence of Reed-Mueller code starting with a positive element. For example, when the signal from the output of the controlled inverter 11 (Fig. 2, and) is multiplied by the Walsh function Wal (10, θ) (Fig. 2, y), a signal is generated at the output of the corresponding multiplier 8 of the first group, which is a sequence of Reed-Muller code S (10, θ) starting with a positive element.

. То есть первый импульс на выходе сформируется через

длительности функций Уолша, второй импульс - через

длительности функций Уолша, третий импульс - через

длительности функций Уолша, четвертый импульс - по завершению длительности функций Уолша (фиг. 3, б). В результате единица, записанная в первом разряде четырехразрядного циклического регистра 13 сдвига последовательно переместится из первого во второй разряд, потом из второго в третий, потом из третьего в четвертый, а затем из четвертого в первый разряд, поскольку регистр 13 сдвига является циклическим.The pulses from the output of the clock generator 1 (Fig. 3, a) are also received at the input of the frequency divider 12, having a division ratio equal to

. That is, the first pulse at the output is formed through

duration of Walsh functions, the second impulse - through

duration of Walsh functions, the third impulse - through

duration of Walsh functions, the fourth impulse - upon completion of the duration of Walsh functions (Fig. 3, b). As a result, the unit recorded in the first bit of the four-bit cyclic shift register 13 moves sequentially from the first to the second bit, then from the second to the third, then from the third to the fourth, and then from the fourth to the first bit, since the shift register 13 is cyclic.

During the first quarter of the duration of the formation of the Walsh functions, the unit is in the first category of the four-digit cyclic shift register 13. In this case, the first additional key 14 is in the open state (Fig. 3, d), and the remaining additional keys are in the closed state. As a result, the first quarter of the signal S (2 ^n-1 -3, θ) generated at the output of the (2 ^n-1 -2) -th multiplier of the first group will arrive at the first information input of the four-input adder 18. In the case 2 ⁿ = 16, this will be the signal S (5, θ) (Fig. 3, c).

During the second quarter of the duration of the formation of the Walsh functions, the unit is in the second category of the four-digit cyclic shift register 13. In this case, the second additional key 15 is in the open state (Fig. 3, e), and the remaining additional keys are in the closed state. As a result, the second quarter of the signal S (2 ^n-1 -5, θ), generated at the output of the (2 ^n-1 -4) th multiplier of the first group, is received at the second information input of the four-input adder 18. In the case 2 ⁿ = 16, this will be the signal S (3, θ) (Fig. 3, d).

During the third quarter of the duration of the formation of the Walsh functions, the unit is in the third category of the four-digit cyclic shift register 13. In this case, the third additional key 16 is in the open state (Fig. 3, h), and the remaining additional keys are in the closed state. As a result, the third quarter of the signal S (2 ^n-1 + 1, θ), generated at the output of the (2 ^n-1 + 2) -th multiplier of the first group, is received at the third information input of the four-input adder 18. In the case 2 ⁿ = 16, this will be the signal S (9, θ) (Fig. 3, g).

During the fourth quarter of the duration of the formation of the Walsh functions, the unit is in the fourth category of the four-bit cyclic shift register 13. In this case, the fourth additional key 17 is in the open state (Fig. 3, k), and the remaining additional keys are in the closed state.

The signal S (2 ^n-1 , θ) generated at the output of the (2 ^n-1 +1) th multiplier of the first group (Fig. 3, i) is input to the delay element 19, as a result of which the specified delay element 19 the signal appears with a delay of one clock cycle (Fig. 3, d).

The delay element 19 is a typical memory element of discrete devices. In the delay element, the value of the output signal at time t + 1 coincides with the value of the input signal at time t.

A detailed description of the delay elements of this type is presented in many sources, including, for example, on pages 231-232 of the publication edited by G.F. Grinenko "Fundamentals of discrete technology ACS and communications" - L .: VIKI, 1980, p. 467).

As a result, the fourth information input of the four-input adder 18 will receive a part of the delayed signal generated at the output of the delay element 19, and at the output of the key 17, a signal segment shown in (Fig. 3, k) will be formed.

The signal generated at the output of the four-input adder 18 is a generating sequence Stif (0, θ) of the Stiffler code. For example, for case 2 ⁿ = 16, the generating sequence Stif (0, θ) of the Stiffler code (Fig. 3, l) has the form:

To obtain, for example, the Stiffler code sequence Stif (10, θ) (Fig. 3, n), the Walsh function Wal (10, θ) (Fig. 3, m) is multiplied elementwise by the generating sequence Stif (0, θ) (Fig. 3, k) in the corresponding multiplier 9 of the second group.

In FIG. 2 are diagrams illustrating, as an example, the process of generating in the proposed signal generator S (10, θ) at the output of the corresponding multiplier 8 of the first group.

In the diagrams of FIG. 2 indicates a temporary state:

a) the output of the clock generator 1;

b) the second output of block 2 of the formation of Walsh functions, on which the function Wal (1, θ) is generated;

c) the sixth output of the Walsh function generation unit 2, on which the function Wal (5, θ) is generated;

d) the twelfth output of block 2 of the formation of Walsh functions, on which the function Wal (11, θ) is generated;

d) key output 6;

e) key output 5;

g) the output of the two-input adder 7;

h) the output of the senior bit 2 ^n-1 - bit cyclic shift register 10;

i) the output of the controlled inverter 11;

j) the eleventh output of block 2 of the formation of Walsh functions, on which the function Wal (10, θ) is generated;

j) the output of the eleventh multiplier 8 of the first group, on which the function S (10, θ) is formed.

In FIG. Figure 3 shows diagrams illustrating, as an example, the process of generating the Stifler code sequence Stif (10, θ) in the proposed generator.

In the diagrams of FIG. 3 indicates a temporary state:

a) the output of the clock generator 1;

b) the output of the frequency divider 12;

c) the output of the sixth multiplier 8 of the first group, on which the signal S (5, θ) is generated;

d) the output of the first additional key 14, on which the first quarter of the signal S (5, θ) is generated;

d) the output of the fourth multiplier 8 of the first group, on which the signal S (3, θ) is generated;

e) the output of the second additional key 15, on which the second quarter of the signal S (3, θ) is generated;

g) the output of the tenth multiplier 8 of the first group, on which the signal S (9, θ) is generated;

h) the output of the third additional key 16, on which the third quarter of the signal S (9, θ) is generated;

i) the output of the ninth multiplier 8 of the first group, on which the signal S (8, θ) is generated;

j) the output of the delay element 19, on which a signal shifted by one clock cycle is generated;

k) the output of the fourth additional key 17, which forms part of the shifted signal;

k) the output of the four-input adder 18, on which a signal is generated, which is a generating sequence of the Stiffler code Stif (0, θ);

m) the eleventh output of block 2 of the formation of Walsh functions, on which the function Wal (10, θ) is generated;

m) the output of the eleventh multiplier 9 of the second group, on which the Stifler code sequence Stif (10.0) is formed.

Thus, the proposed Stiffler code sequence generator has advanced functionality, which consists in the formation of Stiffler code sequences, and can be used to create generator equipment for multi-channel communication systems, including those using LTE technology, for constructing information and information and communication systems for various purposes.

Claims (1)

A Stiffler code sequence generator containing a clock, a Walsh function generation unit, a pulse shaper, a trigger, two keys, an adder, 2 ⁿ multipliers of the first group (2 ⁿ is the number of outputs of the Walsh function generation unit), 2 ⁿ multipliers of the second group, 2 ^{n- 1} - bit cyclic shift register and controlled inverter, frequency divider, cyclic four-bit shift register, four additional keys and four-input adder, and the output of the clock generator is connected to the clock input of the unit Walsh functions, the output of the pulse shaper is connected to the counting input of the trigger, the inverse and direct outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of the first and second keys are connected to the inputs of the adder, the outputs of the block for generating Walsh functions are connected to the second inputs of the corresponding multipliers of the first groups, the second output of the Walsh function generation unit is connected to the input of the pulse shaper, the adder output is connected to the information input of the controlled inverter, -governing input of which is connected to the output of the most significant bit 2 ^n-1 - bit cyclic shift register, a clock input connected to the output of the clock generator, the output control inverter connected to the first inputs of the multipliers of the first group, the outputs of the block forming the Walsh functions are connected to second inputs of corresponding multipliers second group, (2 ⁿ -4) th output and (2 ^n-1 -2) th Walsh functions output forming unit are connected respectively to the data inputs of the first and second keys, the clock output is connected the input of the frequency divider, the output of which is connected to the clock input of the cyclic four-bit shift register, the outputs of the bits of which are connected to the control inputs of the corresponding additional keys, the outputs of the additional keys are connected to the inputs of the four-input adder, the output of which is connected to the first inputs of the multipliers of the second group, characterized in that in order to expand the functionality of the generator, consisting in the formation of stiffler code sequences, a delay element was introduced into it , Wherein the outlet (2 ^n-1 -2) th multiplier of the first group is connected to the data input of the first additional key output (2 ^n-1 -4) th multiplier of the first group is connected to the data input of a second additional key, the output (2 ^{n -1} +2) of the first multiplier of the first group is connected to the information input of the third additional key, the output of the (2 ^n-1 +1) of the first multiplier of the first group is connected to the input of the delay element, the output of the delay element is connected to the information input of the fourth additional key, outputs multipliers of the second group are generator outputs on which Stiffler code sequences are generated.

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