SU947972A1 - Decimal counter - Google Patents

Description

The invention relates to automation and computer engineering and may find application in frequency division devices.

Known decimal counter containing four digits, the logical element And, and performing the division of the input frequency simultaneously into two and ten [1].

The disadvantage of this decimal counter is the small number of division factors.

Closest to the proposed one is a decimal counter containing four digits and two logic elements, the clock inputs of the digits being connected to each other and the input pulse bus, the first inputs of the first groups of inputs via And connected to each other and to the direct output of the fourth digit, whose inverse output is connected to the first inputs of the second groups of inputs connected by AND of logic elements interconnected, the direct and inverse outputs of the first category are connected respectively to the second inputs of the first and second groups of inputs And the first logical element, connected by its output to the J- and K-inputs of the second connected to each other and to the first J- and K-inputs of the third and fourth digits, the second J- and K-inputs of which are connected to each other and to the output of the second logical element, the second inputs of the first and second groups of inputs on And which are connected respectively to direct and in. _n population-inverted outputs of the second category, ^ιυ 'direct output of the third discharge connected to a third connection between the J- and K-inputs of the fourth digit. The device provides for dividing the input frequency simultaneously at 15 two, five and ten [2].

The disadvantage of this device is the small number of division factors of the input frequency.

The purpose of the invention is the expansion of functionality, i.e. obtaining an additional division factor of two and a half.

This goal is achieved by the fact that in the decimal counter containing 25 four digits and two logic elements, the first inputs of the first groups of inputs along And which are interconnected and with a direct output of the fourth category, the inverse output of which 30 is connected to the first connected between the second groups inputs of AND of logical elements, direct and inverse outputs of the first category are connected respectively to the second inputs of the first and second groups of inputs of AND of the first logical element, connected by its output to connected m I am waiting for the J- and K-inputs of the second category and the first J-and K-inputs of the third category, the second J-and K-inputs of which are interconnected and with the U output of the second logic element connected to the second inputs of the first and second groups of inputs by And, respectively, to the direct and inverse outputs of the second category, the 15th input of which is connected to the clock input of the other three bits connected to each other and the input pulse bus, an equivalence element and a three-input logic element And are introduced, with the first input ^{and the} equivalence element in it is connected to the input pulse bus, the second to the output of the second logical element, the output of the first logical element is connected to the first input of the three-input ²⁵ And element, the second input of which is connected to the direct output of the third category, the third to the output of the equivalence element, and the output to the connected between themselves J- and K-vhs-30 ladies of the fourth category.

Figure 1 shows the functional diagram of the decimal counter; figure 2 - diagrams of his work. 35 'The decimal counter contains bits 1-4, element 5 of equivalence, logic elements b and 7, and a three-input logic element And 8, and the clock inputs of bits 1-4 dd and the first input of element 5 of equivalence are connected to each other and to the input pulse bus, the first the inputs of the first groups of inputs by AND of logic elements 6 and 7 are interconnected and with a direct output of discharge 4, the inverse output of which is connected to the first inputs of the second groups of inputs of I and logic elements b and 7 connected to each other, the second inputs of the first and second groups of inputs 50by AND of logic element b, respectively, are connected to the direct and inverse outputs of discharge 1, the output of logic element b is connected to interconnected J-and K-inputs 55 pg ^ of row 2, the first J- and K-inputs of discharge 3 and the first input of logic element And 8, the direct and inverse outputs of discharge 2 are connected respectively to the second inputs of the first and '60 second groups of inputs of an AND element of a logic element 7 connected by its output to connected to the second input of the element of equivalence 5 and the second J- and K-inputs of discharge 3, direct output of which connected to the second input of the AND 8 logic element, connected by its third input to the output of the equivalence element 5, and the output to the J- and K-inputs of discharge 4 interconnected.

The operation of the device is illustrated by the timing diagrams shown in figure 2.

The input pulses (9) are fed to the clock inputs of bits 1-4 and the first input of the equivalence element 5. The input frequency divided by two is formed at the output of discharge 1 (10), by two and a half - at the output of the three-input logic element 8 (16), by five - at the output of discharge 3 (14), by ten - at the output of discharge 4 (17) . Waveforms at the outputs of discharge 2, logic elements. 6 and 7 and the equivalence element 5 are shown in (12), (13) and (15), respectively.

Thus, the proposed decimal counter compares favorably with the known number of frequency division coefficients, which greatly expands its functionality.

Claims (2)

1. gutnikov B.C. Integrated electronics in measuring devices. M., Energie, 1980, p.213, . fig.14-16. 2. The author's certificate of the USSR, № 646433, cl. H 03 K 23/02. uz.2.