SU1201836A1 - Device for calculating modulus of vector - Google Patents

Abstract

A DEVICE FOR CALCULATING A VECTOR MODULE containing the first and second counters, accumulating a cyclic transfer adder, a pulse generator, the first and second delay elements, the first element And the group of elements And, the outputs of which are connected to the outputs of the result of the device, the first inputs of the elements And group are connected to direct outputs of the corresponding bits of the first counter, the inverse outputs of the bits of which are connected to the first group of information inputs of the accumulating adder with cyclic transfer, the second group The pa of information inputs of which are connected to the direct outputs of the bits of the second counter, the output of the first element I is connected to the input of the first delay element and the first input of the accumulator with cyclic transfer, and the first input to the output of the pulse generator, characterized in that In order to improve speed, the second and third elements AND, two triggers and the OR element are entered into the device, the second inputs of the AND elements of the group are connected to the outputs of the direct values of the second counter, the outputs of the first and second elec The delay delays are connected to the counting inputs of the corresponding counters, the overflow outputs of which are connected to the inputs of the OR element, whose output1 is connected to the third inputs of the AND elements of the group and to the zero inputs of the first and second triggers, the first input of the second element AND is connected to the output of the pulse generator, and the output is to the input of the second delay element and the second input of the record accumulating adder with cyclic transfer, the outputs of the signs of the negative and positive values of which are connected (L with the second inputs respectively, the second and first elements And, the third inputs of which are connected to the direct output of the first trigger, a single input of which is connected to the start input of the device and the first input of the third And element, the second input of which is connected to the second input of the first And element, and the output to a single the input of the second trigger, the inverse output of which is connected to the input control of the addition of the first counter and input 00 of the control of subtraction of the second counter, with the direct output of the second trigger is connected to the O5 input of the control of subtraction of the first of the counter and the control input of adding the second counter.

Description

The invention relates to automation and computing and can be used in specialized computing devices, for example, to measure the lengths of straight-line segments of semi-automatic input and coding of graphic information using input graphic terminals of the tablet type ...

The purpose of the invention is to increase speed.

The drawing shows the functional scheme of the proposed device.

The device contains counters 1 and 2 accumulating adder 3 with cyclic transfer, the elements And 4 and 5 ,. delay elements 6 and 7, pulse generator 8, trigger 9, AND 10 element, AND trigger, AND 12 element group, OR 13 element, start input 14, result outputs 15.

Reversible counters 1 and 2 are used to store and count the current values of variables, the value of one of which at the end of the calculation cycle takes the value of the vector modulus.

The adder 3 is used to calculate the error function. The direct and inverse OUTPUTS of the sign bit of the adder 3 are, respectively, the outputs of the signs of the negative and positive values of the contents of the adder 3. Elements 4 and 5 are switches of the generator 8 pulses.

The delay elements 6 and 7 are matching links that ensure the correct operation of the device by delaying the signal by the time required to perform the operation in the adder 3.

The pulse generator 8 is used to set the clock frequency of the device. The trigger 9 serves to allocate a working time interval.

Element AND 10 serves to select a signal that determines the state of the sign bit of the adder 3 after the input of the initial data into it.

The flip-flop 11 serves to memorize the state of the sign bit of the adder 3 after inputting the initial data into the adder, and selecting the reversible counters 1 and 2 in accordance with this mode of operation.

The group of elements And 12 serves to produce a result. The number of elements in the group is equal to the number of bits of the counter 1 (2).

The OR 13 element serves to assemble the carry signals that occur when one of the counters 1 and 2, which determine the end of the computation cycle, is zeroed.

The principle of operation of the device is based on the calculation of the mismatch function defined by the expression.

F.-y Fo-Z: (x + i) + i: (Y-) if X Y (f) "t" -x 0434Y

Fij Fo-jgjX-i) + (Y-fj) if X4Y (2)

Here fo y-x

After substituting the values of the upper limits of summation, instead of the values of the variables in the parentheses of expressions (1) and (2), one of the bracket expressions in (1) and (2) turns into zero, and the other will be equal to the desired result

. - Y, with the moment of termination

5 calculations. It coincides with the moment of zeroing one of the bracket expressions IB (I) and (2). For the convenience of fixing this moment of the end of the calculations, it is determined when one of the bracket expressions is changed from plus (-f) to minus (-).

Counting Bracket Expressions

in (1) and (2) is performed by counters 1 and 2,

and the value of the mismatch function (1)

and (2) is calculated by adder 3.

Maximum value of absolute

5 errors in the entire range of the device does not exceed one elementary step ..

The device works as follows.

In the initial state, the counters 1 and 2, the adder 3, and the flip-flops 9 and 11 are reset, while according to the potential at the output of the trigger 11, the counters .1 and 2 are switched to the Summation and Calculation.

5Before starting the device in

counters 1 and 2 enter the values of the initial values X and Y, respectively, and the adder 3 - the value of their difference Y-X. If the value of this difference is less than zero, then the resolving potential at the input of the element And 10, associated with the output of the adder 3, is absent and the pulse from the input 14 to the output of the element And 10 does not pass. The trigger state 11 does not change and the set operating mode of the counters does not change.

5 If the value of the contents of the adder 3 is equal to zero or more, then the enabling signal from the output of the adder will go to the input of the element 10 and the pulse received from the input 14 will pass; to the output of the element And 10 and change the state 0, but not the trigger 11 to the opposite. At the same time, counter I will be turned on to the mode “Subtraction, and counter 2 - to the mode“ Summation. In the process of further work of the trigger 11 of its state,. Neither does it change and, as a matter of fact, fixes the value of the sign bit of the adder 3 after the input of the initial data into it. Changing the reverse of the counters and 2 depending on the contents of the adder 3 is necessary to shorten the calculation cycle. With the arrival at the input of the trigger 9 of the signal from the input 14, the trigger 9 changes its state to the opposite and at its output the enabling signal appears at the inputs of the AND 4 and 5 elements. If the value of the contents of the adder 3 is negative, the resolving potential its output is fed to the input of the element AND 4, which begins to pass at the output pulses arriving at its input from the output of the generator 8 pulses. If the value of the content is zero or positive, then the enabling signal from the output of the adder 3 is fed to the input element And 5, which begins to pass to the output pulses arriving at its input from the generator output 8 pulses, the element 4 is closed. Each pulse coming from the output of the element And 4 to the input of the adder 3, summing the contents of the counter 2 with the contents of the adder. This process continues until the content of the adder is zero or more. As a result, the enable signal at the input of the AND 4 element, associated with the output of the adder 3, disappears, and at the input of the AND 5 element, associated with the output of the adder 3, appears, as a result of which the AND 4 element closes and the And 5 element opens up. The latter begins to transmit pulses from the generator output of 8 pulses to its output. Each pulse coming from the output of the element And 5 to the input of the adder 3, causes the subtraction of the contents of the counter 1 from the contents of the adder 3. This happens until the contents of the adder becomes negative. At the same time, the enabling signal at the input of the AND 5 element, associated with the output of the adder 3, will disappear and the And 5 element will be closed, and the input signal of the 4, connected with the output of the adder 3, will disappear, and the And 4 element will open. Each pulse coming from the output of the element 4 through the element 7 of the input delay of the counter 2 adds or subtracts from the contents of the counter 2, depending on the setting of the initial mode of the counter 2, determined by the state of the adder 3 after the input of the initial data, a single increment . Similarly, each pulse coming from the output of AND 5 through the delay input element 6 of counter 1, subtracts or adds, depending on the initial mode setting of counter 1, determined by the state of adder -3 after inputting the initial data into it, to the contents of the counter 1 unit increment. At the same time, if counter 1, in accordance with the initial data, is included in the Summation mode, then counter 2 is switched on in the Subtraction mode and vice versa. This leads to the fact that a smaller value of the initial value during the operation of the device decreases, and a larger value increases, which reduces the overall computation time. The described work process continues until the value of the contents of one of the counters 1 and, 2 becomes equal to minus one (- 1). This state of the counter will correspond to the presence of enabling signals on all direct outputs of counter 1 and 2 connected to the inputs of elements AND 12. The transfer signal that occurs when the sign changes in the high bit of counter 1 (2) passes through the element OR 13 and goes to the control inputs elements 12, allowing the output of the contents of another counter 2 (1), numerically equal to the modulus of the vector, to the outputs 15 of the result.

Claims (1)

DEVICE FOR CALCULATING A VECTOR MODULE, containing the first and second counters, accumulating an adder with a cyclic transfer, a pulse generator, the first and second delay elements, the first element And and a group of elements And, the outputs of which are connected to the outputs of the device, the first inputs of the elements And groups are connected to direct outputs of the corresponding bits of the first counter, the inverse outputs of the bits of which are connected to the first group of information inputs of the accumulating adder with cyclic transfer, the second group of info the input of which is connected to the direct outputs of the discharges of the second counter, the output of the first element And is connected to the input of the first delay element and the first input of the storage accumulator with cyclic transfer, and the first input is to the output of the pulse generator, characterized in that, in order to improve performance, the device introduced the second and third elements AND, two triggers and an OR element, with the second inputs of the elements of the AND group connected to the outputs of the direct values of the second counter, the outputs of the first and second elements the ki are connected to the counting inputs of the corresponding counters, the overflow outputs of which are connected to the inputs of the OR element, the output of which is connected to the third inputs of the elements of the AND group and to the zero inputs of the first and second triggers, the first input of the second AND element is connected to the output of the pulse generator, and the output to input of the second delay element and the second input of the recording accumulator cyclic pereno- _l catfish, and negative signs outputs po- $ g which positive values are connected to second inputs respectively sec of the first and first elements AND, the third inputs of which are connected to the direct output of the first trigger, the single input of which is connected to the start input of the device and the first input of the third element And, the second input of which is connected to the second input of the first element And, and the output - to the single input of the second trigger the inverse output of which is connected to the input control of the addition of the first counter and the input of the subtraction control of the second counter, the direct output of the second trigger is connected to the input of the subtraction control of the first counter and the control input adding a second counter. ]1