SU1300463A1 - Device for representing polynominals - Google Patents

Abstract

The invention relates to computing and is intended to reproduce polynomials. The purpose of the invention is to increase the accuracy of reproduction of a polynomial with small values of coefficients. The goal is achieved by calculating each of the polynomial members at an optimal scale, which allows increasing the machine coefficient codes so as to fully utilize the length of the discharge grid of device blocks, which is achieved by introducing a device containing a multiplier 16, adder 17, register 14, switch 11 , memory block 9, counter 7, first 3 and second 4 And elements and trigger 1 with corresponding connections, second register 15, third 5 and fourth 6 And elements, second counter 8, second memory block 10, second 12 and third its 13 switches and the second trigger 2. 2 ill. ZU (L s

Description

fie.7

one

This invention relates to computing and is intended to reproduce polynomials of the form.

V 21 A. (1)

The purpose of the invention is to increase the accuracy of the reproduction of a polynomial at small values of the coefficients.

Figure 1 shows the functional diagram of the device; Fig. 2 is a sequence diagram of the main control signals.

The device contains the first 1 and second 2 triggers, the first 3 "second

13004632

fixed recording of numbers t -1 and t in the first 7 and second 8 counters is made, respectively, and the passage of clock pulses 5 (TI) 19 from the input of the converter through the second element 4 is prohibited.

At this time, the signal P2 at the output of the second flip-flop 2 is also equal to O, which determines the presence of O at the outputs of the elements I 5 and 6, as well as the argument codes X at the outputs of the second switch 12 and the coefficient a at the outputs of the third switch 13, since PZ signal at the output of the first ele4, third 5 and fourth 6 elements, And, ment And 3 is also equal to O, This sigder 7 and second 8 counters, the first 9 and second 10 memory blocks, the first 11, the second 12 and third 13 switches, the first 14 and 15 second registers, multiplier 16, adder 17, start inputs 18, clock pulse 19, argument code 20 and the coefficient code 21, the output of the sign of readiness of the result 22.

On the cyclogram high level

signal corresponds to O,

 R

and low

The device implements the following algorithm:

a + b, x. (a, + bc (a + x (a „., +) ,,,)),

(2)

where b ,, ,, ,,, ЬЬ, are the rescaling coefficients, taking into account the difference in the scales of representation of the coefficients a ,,. ,, ,, a.

A start pulse (OF) 18 (with a frequency f of) starts a calculation cycle, synchronized with clock pulses (TI) 19, with a frequency of f 2m E out, and the duration of IZ 18 and TI 19 coincides. During each clock cycle, a multiply operation is performed on a parallel a combinational multiplier 16, the result of which is entered at the end of a clock in the second register 15.

In the even-numbered cycles of operation of the device, an addition operation is performed on the parallel combiner adder 17.

Before the next computation cycle begins, the output of the first trigger 1 has a signal O, which is passed to the control input of the first switch 11, the second group of inputs of which receives the function code F17, and the first group the coefficient code a from the inputs 21 of the converter. The first switch 11 generates at its outputs the function code F11 in accordance with the expression

25

Fll

"GP PZ,

From converter inputs 20, the argument code X is fed to the second group of inputs of the second switch 12, the second group of inputs of which is

the code of the coefficient bm sticks out from the second block of 10 memory, and to the control input - a sequence of signals P12 from the output of the second flip-flop 2;

mutator 12 generates at its outputs the function code F12 in accordance with the ratio

F12 X P2 + P2.

The function code F12 goes to the first group of inputs of the multiplier 16, to the second group of inputs of which from the outputs of the third switch 13 receives the function code F13, and to the control input - a sequence of pulses PI4 from the output of the second element 4,

The multiplier 16 codes F12 and F13 produces pulses PI4 code

 F16 in accordance with the expression

F16 F12 F13,

From the outputs of the first switch 11, the function code F11 is fed to the first group of inputs of the third switch 13, to the second group of inputs of which the function F16 is fed, and to the control input is a sequence of signals

112 from the output of the second trigger 2. According to the listed signals, the third switch 13 forms at its outputs the function F13 in accordance with the expression

F13 Fll ifZ + G16-.P2.

From the outputs of the first 7 and second 8 counters, the codes of the numbers t -1 and t arrive at the corresponding address inputs of the first 9 and second 10 memory blocks. The first block of memory 9 contains the codes of the coefficients of the polynomial

am-t, and ,, Eo and by code

t-1 it produces at its outputs a coefficient code a,, arriving at the first group of inputs of the adder 17.

In the second memory block 10, the coefficients of the scaling coefficients b, bfn., ,,. ,, a ,, b, b are contained, and at code m it produces at its outputs a code of coefficient b, which arrives at the second group of inputs of the second switch 12.

For example, when using the proposed converter for linearizing and rationing the characteristics of precision primary information sensors, the coefficients b, ..., b are chosen to be constant for this type of sensor, and the coefficients a ,,., And determine the individual differences in the characteristics of a particular sensor sample from a linear one. . If it is necessary to replace the sensor, the contents of the memory block 9 are also changed; therefore, it is often performed reprogrammed.

The device works as follows.

The calculation cycle starts with the input from the start of input 18 of the converter, alternately, of a start pulse (IZ) 18, according to which the operation of the first element I 3 is prohibited (i.e. at the moment of action IZ 18 of the PZ-0), and the first trigger 1 is set to 1, which removes the fixed record signal from counters 7 and 8 and permits the passage through the second element of AND 4 clock pulses TI 19 from the input 19 of the converter.

At the same time, at the output of the second element, AND 4, the sequence of clock pulses pi 4 begins to be produced by TI 19, the first pulse of which coincides with the pulse OF 19 and the number of pulses is 2m.

This sequence goes to the direct inputs of the third 5 and fourth 6 elements And, to the clock (synchronizing) input of the second trigger 2 and the control input of the multiplier 16. At the output of trigger 2, a sequence of pulses P2 appears, which goes to the control inputs of the second 12 and the third 13 Switches, as well as to the inverse and direct inputs of the third 5 and fourth 6 AND elements, respectively.

Since the leading edges of the P2 pulse are delayed relative to the rising edges of PI4, two other sequences of PI 5 and PI 6 pulses are formed at the outputs of the third 5 and fourth 6 elements And

The sequence of PI 5 contains m pulses coinciding in time with the odd pulses of PI 4, and is fed to the subtracting input of the first counter 7 and the control inputs of the first register 14 and the adder 17.

At the moment after the end of the first calculation cycle (first PI 4 and PI 5 pulses), the second counter 8 goes to the state t -1, the second code 15 records the code y, and the output of the first element And 3 sets the signal PZ 1, which remains unchanged throughout the entire cycle of calculations. By the end of the second calculation cycle (first PI 6 pulse), the first counter 7 enters the state t-2, the code y, y, b + a is entered into the first register.

After the end of the third calculation cycle (the second PI 5 pulse or the third PI 4), the second counter 8 goes to the state t-2, the code is entered into the second register 15

Ug Y, X.

Further, the calculation process is repeated as described.

At the moment of the last pulse of the PI 4 sequence (or t pulse of the PI 6 sequence), the polynomial code Ugg, (2) is generated at the outputs of the adder 17, and at the overflow output of the first counter 7, an overflow pulse is generated AND 7, which is used to record the result of the calculation from the outputs of the adder 17. From the first counter 7, the I7 also enters the counting input of the first trigger 1.

At the moment of action of I7, the last impulse PI 6 acts on the control input of the first register 14.

In connection with this, at the moment after termination of I7, the triggers 1 and 2 are set to O, and in the first register 14 the code is written from the outputs of the adder 10. This completes the calculation cycle.

Therefore, at any time the time interval between the end of the queue-I7 and IZ 18c of the first register 14 can be removed the result of the previous cycle of calculations - the code

Claims (1)

Invention Formula A device for playing polynomials containing a multiplier, an adder, a first register, a first switch, a first memory block, a first counter, first and second And elements, and a first trigger whose clock input is a device start input and connected to the first inverse of the first And element The output of which is connected to the control input of the first switch, the first information input of which is the input of the device coefficient code, the output of the first trigger is connected to the second and first inputs of the first and second elements And, respectively, with the counting input of the first counter, the overflow output of which is the output of the readiness indication result of the device and connected to the clock input of the first trigger, the information output of the first counter connected to the address input of the first memory block, the output of which is connected to the input of the first addend the adder, the input of the second term of which is connected to the output of the multiplier, the output of the adder is the information output of the device, and the connection 45 and I is connected to the clock input with information the input of the first counter and the input of the register synchronization, the output of which is connected to the second informator; the ionic input of the switch; the second input of the element I is the clock input of the device, which is In order to increase the accuracy of reproducing the value of a polynomial at small values of coefficients, a second register, third and fourth elements AND, a second counter, a second memory block, second and third switches, and a second trigger, whose output is connected to the control inputs of the second and the third switch, with the first inverse of the third And with the first input of the fourth element And whose output is connected to the clock input of the first counter and synchronization inputs of the adder and the first register, the output of the first trigger is connected to the second input of the third element And the counting input of the second counter, the information output of which is connected to the address input of the second memory block output which is connected to the first information input of the second switch, the second information input of which is the input of the device argument code, the output of the second element AND is connected to the clock input of the second trigger, the third and third inputs of the third and fourth elements AND, respectively, the synchronization input of the multiplier, the multiplier input koto connected to the output of the second switch, the output of the first switch is connected to the first information input of the third switch, the output of which is connected to the multiplicator input, the output of which is connected to the information input of the second register, the output of which is connected to the second information input of the second switch, third output second register. Editor T. Mitejko Compiled by N.Matveev Tehred I.Popovich Proofreader E.Roshko Order 1149/47 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 FIG. 2