SU1305670A1 - Device for calculating values of n-th order polynominal - Google Patents

Abstract

The invention relates to computing and can be used in measuring and computing systems operating in real time. In order to increase the speed of the device when calculating polynomials with the same coefficient values and different argument values, the device contains elements 5, counter 8, blocks 9, 10 of memory, adders 11, 12, switches 13, 14, register multiplexer 15 multipliers. 19, 20, entered registers 16-18, triggers 1-4 and elements 6, 7, 4, 4, etc.

Description

The invention relates to computing and can be used in measuring and computing systems operating in real time.

The purpose of the invention is to increase the speed of the device when calculating polynomials with the same coefficient values and different argument values.

Fig, 1 shows a functional diagram of the device; FIG. 2 shows the cytogram of its operation; on FIG. 3 - the temporary diagram of operation of triggers; figure 4 - triggers.

The device contains triggers 1-4, elements And 5-7, counter 8, memory blocks 9 and 10, adders 11 and 12, switches 13 and 14, register-multiplexer 15, registers 16-18, multipliers 19 and 20, start inputs 21, synchronization 22, the values of degree 23 and argument 24, the outputs of information 25 and the end of work 26 signal.

The diagram (FIG. 2) shows the synchronization pulses 27 and the start 28 states at the outputs: 29 - the first trigger 1, 30 - the second trigger 2, 31 - the second element And 6, 32 - the counter is charged, 33 - the first element And 5, 34 - the third element And 7, 35 - the re- Jistra-miltiplatopa 15, 36 - the third of its trigger 3, 37 - the fourth trigger 4.

The device implements an algorithm for calculating polynomials by the formula

 ... (.2). .., + + ... (a.) ....

The device works as follows.

In the initial state, in the first memory block 9, the values of the coefficients a.1 are placed, and

rum block 10 beneficiaries

p-3

0,

in the BTO, 45 multiplier outputs, and recorded

memory - values of

P

Counter 8

is in zero state.

Input 21 receives a Start signal, according to which the first trigger 1 generates a pulse T1 with a duration equal to the period of sync signals (SI), under which the trigger 2 triggers the pulse T2 received through the AND 6 element to the counting input of the counter 7. At the same time The loan at the output of the counter goes from zero to zero. The loan amount is fed to the input of the first element

with the arrival of the SI in the first 16 and second 1 registers, respectively. In the next cycle of the device, the coefficients a. fi arrive at the inputs of the first

50 19 and 20 second multipliers, where they are multiplied by the value (X1) 2, and then they are added to the first 11 and second 1 adders with the readings from the address (n - 1) / 2 - 1 from the first 9 and second 1

55 memory blocks with a-and-coefficients. . The results of the summation of the records are recorded respectively in the first 16 and second 17 registers. In the following tat results removed from the outputs

five

0

five

0

five

And 5, allowing the passage of the SI to the counting input of the counter 8.

The inverse of the size of the loan is given to the input of the TI element 7, prohibiting the SI from passing to the synchronous input of the register 15 during the counting of the counter 8. At the moment t the register 15 through its second information input is written the value of the argument XI, C register output 15 value argum € nta is fed to the inputs of the first switch 19 (directly to the first input) and through the first switch 14 to the second input. The first switch 14 connects the output of register 15 to the input of the first multiplier 19 for the duration of the pulse T1, which falls on the control input of the first switch 14. From the output of the first morning switch 19, the value (XI) is written to register 15 via its first information input at the moment time t and stored in it until the end of the counting of the counter 8. Recording in the register 15 through the first information input is allowed for the duration of the pulse T1 arriving at its control input. With the arrival of the pulse T1 on the reset inputs of the first 16 and second 17 registers, these registers are zeroed (at time t,) and saved. the zero state is up to the time t. This ensures zeroing of the outputs of the first 19 and second 20 multipliers.

0

from time t, to time tj. At this time interval, the coefficients a p written at address p / 2 are read from the first 9 and second 10 memory blocks, respectively.

These coefficients are added up on the first 11 and second 12 summations with zero values received from

with the arrival of the SI in the first 16 and second 17 registers, respectively. In the next cycle of the device, the coefficients a. fi arrive at the inputs of the first

50 19 and 20 second multipliers, where they are multiplied by the value (X1) 2, and then they are added to the first 11 and second 12 adders with readings from (n - 1) / 2 - 1 from the first 9 and second 10

55 memory blocks with a-and-coefficients. . The summation results are recorded respectively in the first 16 and second 17 registers. In subsequent cycles, the results are removed from the outputs.

The first 16 and second 17 registers are multiplied by the value (X1) and are added with the next readable coefficients as described. The order of counting coefficients from the memory blocks is determined by the counter 8, from the output of which the status code is fed to the control inputs of the memory blocks. When the counter 8 reaches the zero state and with the arrival of the leading edge of the SI, the discharge of the loan at the output of the counter 8 takes a zero value and prohibits the further arrival of clock signals to the counting input

counter 8, the inverse of which the size of the resolution -15 is connected to the output of the first and the loan by the leading edge sets the third trigger 3 to the one state at the moment of time t.

With the arrival of the next SI, the unit value of the third flip-flop 3 of the switch 20 is connected with the first one to the fourth flip-flop 4, the third flip-flop 3 resetting to the zero state with a signal from the inverse output. The next SI translates the fourth triple multiplier, the output of the second multiplier is connected to the input of the first term of the second adder and the first data input of the register-multiplexer, the extraction input of the second switch, the output of which is connected to the input of the multiplicand second multiplier, of which for the purpose of loss 4 to the zero state.

Thus, a T4 pulse is generated. The changed loan bit value at the output of counter 8 again allows the SI to pass to the input of register 15, which accepts the value of the argument X1 by the time tf. Pulse T4 from the fourth trigger 4 is fed to the control input of the second switch 14, providing for the duration of the pulse T4 connecting the output of the first register 16 to the second input of the second adder 12. The first input of the second adder 12 receives the result from the second register 17, the jack on the second multiplier 20 on the value of the argument X1. From the output of the second adder 12, the value of a nth-degree polynomial is written to register 18 on the trailing edge of the pulse.

the inverse output of the counter's discharge is connected to the second inverse input

Claims (1)

T4. From the output of register 18, the value is –45 with the synchronous input of the counter, the parallel line is taken to the output 25 whose data input is input. In addition, an output T4 from the output of the fourth flip-flop 4 is outputted to the output device 26 of the device’s exponent. The leading edge impulse T4 indicates the possibility 50 of the first And element, the second feed input to the input 24 of the new Andor element and the input —gument (e.g., X2) and the Start-to-Signal signal 24. The trailing edge of the T4 pulse informs that the calculation of the polynomial has been completed. 55 claims The fourth trigger, the output of which is connected to the information input of the third trigger, the output of which is the output of the device’s cycle end signal and is connected to the control input of the first switch, the reset input of the fourth trigger and the synchronization input of the third register A device for computing a polynomial of degree n containing two blocks memory, two adders, two switches, two multipliers, a register-multiplexer, a counter and the first And element, the first input of which is the device synchronization input, the output of the first And element is connected to the counter input of the counter, the information output of which is connected to the address inputs of the first and the second memory block, the output of the first memory block is connected to the first information input of the first switch, the output of which is connected to the input of the first term of the first adder, the input of the second term which is connected to the output of the first the course of which is connected to the first information multiplier, the output of the second multiplier is connected to the input of the first term of the second adder and the first data input of the register-multiplexer, the output of which is connected to the first information the second input of the switch, the output of which is connected to the input of the multiplicand second multiplier, which is so that, in order to increase the speed of the device when calculating polynomials with the same values of coefficients and different values of the arguments, It has four triggers, the second and third And elements, three registers, the first inputs of the second and third And elements, and the synchronous inputs of the first and second registers and the first to third triggers are connected to the synchronization input the device, the information input of the first trigger is the start input of the device, the first trigger input is connected to the control inputs of the multiplexer register and the second switch, the first and second register reset inputs and the second trigger information input, the output of which is connected to the second input of the second element, output which is connected the inverse output of the counter's discharge is connected to the second inverse input with the synchronous input of the counter, the parallel data input of which is the input of the exponent of the device, the first element AND, the second input of the third element AND and the input of the set with the synchronous input of the counter, the parallel data input of which is the input of the exponent of the device, the first element AND, the second input of the third element AND and the input of the set The fourth trigger, the output of which is connected to the information input of the third trigger, the output of which is the output of the device’s cycle end signal and is connected to the control input of the first switch, the reset input of the fourth trigger and the synchronization input of the third register 5. 1305670 pa, the output of which is the information output of the device, the output of the first adder is connected to the information inputs of the second and third registers, the output of the second register is 5 connected to the input of the multiplicand first multiplier, the output of the second memory block is connected to the input of the second term of the second adder, the output of which the first register, the output of which is not the second information of the first and the second commutator of the third element And the synchronization register register, the output of which is connected by the multiplier of the first and the second, connected to the information input of the first argument of the device. register, the output of which is connected to the second information inputs of the first and second switches, the output of the third element I is connected to the synchronization input of the register-multiplexer, the output of which is connected to the inputs of the multiplier of the first and second multipliers, the second information input of the register-multiplexer is 35 35 37 ti tz Fshg  " 35ns. Editor N.Rogulich Order 1452/46 Compiled by N.Matveev Tehred; l.0leynik Proofreader A.Zimokosov Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35 Raushsk nab. 4/5 Production and printing company, Uzhgorod, Projecto st., 4 FIG.