SU1264200A1

SU1264200A1 - Digital correlator

Info

Publication number: SU1264200A1
Application number: SU843790393A
Authority: SU
Inventors: Валерий Константинович Богушевич; Михаил Иванович Скипа; Александр Вадимович Холопцев
Original assignee: Одесское Отделение Морского Гидрофизического Института Ан Усср
Priority date: 1984-08-01
Filing date: 1984-08-01
Publication date: 1986-10-15

Abstract

Изобретение относитс к вычислительной Технике и предназначено дл коррел ционной обработки сложных сигналов в задачах гидролокации, вигации, командоуправлени и передачи информации. Цель изобретени повьшение быстродействи . Сущность изобретени заключаетс в использовании дл достижени поставленной цепи принципа обработки по част м. Общий объв выборок принимаемого сигнала делитс на равные части, обрабатьшаемыёпараллельно во времени. Дл реализации этого принципа устройство дополнительно содержит второй элемент задержки, одновибратор, второй и третий счетчики с соответствующими функ1щональньв4и св з ми между ними и известными блоками корСО рел тора . 1 ил. С toThe invention relates to computer engineering and is intended for the correlation processing of complex signals in the tasks of sonar, navigation, command and transmission and information transfer. The purpose of the invention is to improve speed. The essence of the invention is to use the principle of processing in parts to achieve the set chain. The total sample of the received signal is divided into equal parts, processed in parallel with time. In order to implement this principle, the device additionally contains a second delay element, a one-shot, second and third counters with corresponding functionalities and connections between them and known blocks of the correlator box. 1 il. From to

Description

Изобретение относится к вычислительной технике, предназначено для корреляционной обработки сложных сигналов, и может быть использовано в системах навигации, командоуправления и передачи информации.The invention relates to computer technology, is intended for correlation processing of complex signals, and can be used in navigation systems, command control and information transfer.

Цель изобретения - повышение быстродействия.The purpose of the invention is improving performance.

На чертеже представлена структурная схема цифрового коррелятора.The drawing shows a structural diagram of a digital correlator.

Коррелятор содержит аналого-цифровой преобразователь 1, второй коммутатор 2, первую группу элементов 3 памяти, третий счетчик 4, второй счетчик 5, первый коммутатор 6, группу блоков 7 умножения, вторую группу 8 элементов памяти, первый счетчик 9, второй элемент 10 задержки, элемент И 11, генератор 12 тактовых импульсов, первый элемент 13 задержки, сумматор 14, регистр 15, одновибратор 16, информационный вход 17 коррелятора, выход 18 коррелятора.The correlator comprises an analog-to-digital converter 1, a second switch 2, a first group of memory elements 3, a third counter 4, a second counter 5, a first switch 6, a group of multiplication blocks 7, a second group of 8 memory elements, a first counter 9, a second delay element 10, element 11, clock generator 12, first delay element 13, adder 14, register 15, one-shot 16, correlator information input 17, correlator output 18.

Работа коррелятора основана на принципе обработки сигнала по частям, который заключается в делении общего числа выборок принимаемого сигналами соответственно опорного) на н равных частей и обработке этих частей одновременно, параллельно во времени. При этом операция вычисления одного значения функции корреляции, заключающаяся в нахождении суммы произведений всего числа выборок, принимаемого и опорного сигналов, заменяется операцией одновременного нахождения сумм произведений отдельных частей об1цего числа выборок принимаемого и опорного сигналов с последующим суммированием получаемых частных результатов. В этом случае время обработки всего сигнала определяется временем обработки отдельной его части и не зависит от количества обрабатываемых параллельно частей.The work of the correlator is based on the principle of processing the signal in parts, which consists in dividing the total number of samples received by the signals, respectively, reference) into n equal parts and processing these parts simultaneously, in parallel in time. In this case, the operation of calculating one value of the correlation function, which consists in finding the sum of the products of the total number of samples, the received and reference signals, is replaced by the operation of simultaneously finding the sums of the products of individual parts of the total number of samples of the received and reference signals, followed by summing the obtained partial results. In this case, the processing time of the entire signal is determined by the processing time of its individual parts and does not depend on the number of parts processed in parallel.

Коррелятор работает следующим образом.The correlator works as follows.

С выхода генератора 12 тактовые импульсы поступают на вход счетчика 4 и через элемент И 11 - на вход счётчика 9. Весь процесс вычисления одного значения функции корреляции происходит за (N/n) + 1 тактов. Последовательное изменение состояний счетчиков 4 и 9, адресные выходы которых соединены с адресными входами | элементов 3 и 8 памяти, обеспечиваетFrom the output of the generator 12, the clock pulses are fed to the input of the counter 4 and through the element 11 to the input of the counter 9. The whole process of calculating one value of the correlation function takes place in (N / n) + 1 clock cycles. Successive change of states of counters 4 and 9, the address outputs of which are connected to the address inputs | elements 3 and 8 of memory, provides

СЮ 2 последовательное извлечение информации из них, т.е. рециркуляцию частей принимаемого и опорного сигналов. Счетчики 4 и 9 имеют равное число рабочих состояний (N = N/n), определяющих соответственно число используемых элементов 3 и 8 памяти. С выхода счетчика 4 сигнал поступает на первый (суммирующий) вход счетчика 5. Этот счетчик имеет число рабочих состояний, равное числу элементов 3 памяти и указывает номер элемента, в котором хранится предыдущая выборка сигнала. Счетчик 5 совместно со счетчиком 4 фактически представляет собой счетчик адреса всех элементов 3 памяти, используемых для хранения принимаемого сигнала. С управляющего выхода счетчика 9 на его Ν’-м рабочем такте (импульс переноса) сигнал поступает на входы элемента 10 задержки и одновибратора. 16. На следующем N¹ + 1-м такте генератор 12 тактовых импульсов через элемент 10 задержки подает сигнал на вход разрешения вычитания счетчика 5. На этом же такте одновибратор 16 подает сигнал на элемент И 11 и блокирует (запрещает) прохождение N + 1-го тактового импульса на вход счетчика 9.SSC 2 sequential extraction of information from them, i.e. recirculation of parts of the received and reference signals. Counters 4 and 9 have an equal number of operating states (N = N / n), which respectively determine the number of used memory elements 3 and 8. From the output of counter 4, the signal goes to the first (summing) input of counter 5. This counter has the number of operating states equal to the number of memory elements 3 and indicates the number of the element in which the previous signal sample is stored. The counter 5 together with the counter 4 is actually an address counter of all memory elements 3 used to store the received signal. From the control output of the counter 9 at its Ν'th working cycle (transfer pulse), the signal is supplied to the inputs of the delay element 10 and the single-shot. 16. At the next N ¹ + 1-th clock, the clock generator 12 through the delay element 10 sends a signal to the input of the subtraction of the counter 5. At the same clock, the single-shot 16 sends a signal to the And 11 element and blocks (prohibits) the passage of N + 1- th clock pulse to the input of the counter 9.

Этим достигается сдвиг в течение цикла корреляции на единицу нумерации элементов 3 памяти относительно нумерации элементов 8 памяти, т.е. эффект продвижения принимаемого сигнала относительно опорного. За ι время цикла корреляции счетчик 9 последовательно изменяет свои состояния от 1-го до N¹-го и опять приходит в 1-е состояние.This achieves a shift during the correlation cycle by the unit of numbering of the memory elements 3 relative to the numbering of the memory elements 8, i.e. the effect of advancing the received signal relative to the reference. During ι the time of the correlation cycle, the counter 9 sequentially changes its state from the 1st to the Nth ^1st and again comes to the 1st state.

Счетчик 4 за это время изменяет свое состояние от начального г-го до N -го, далее 1-го и в конце цикла корреляции приходит в г + 1-е состояние. На этом ν' + 1 такте через элемент 10 задержки подается сигнал на управляющий вход регистра 15, осуществляется выдача вычисленного значения функции корреляции. Подается сигнал на вход элемента 13 задержки, а через него - на управляющий вход «умматора 14, осуществляя обнуление последнего и подготовку к работе в новом цикле корреляции. Подается сигнал на тактовый вход коммутатора 2, производя запись новой выборки принимаемого сигнала в соответствующий элемент 3 памяти.Counter 4 during this time changes its state from the initial nth to the Nth, then the 1st and at the end of the correlation cycle it comes to the g + 1st state. At this ν '+ 1 clock cycle, a signal is supplied through the delay element 10 to the control input of the register 15, and the calculated value of the correlation function is output. A signal is supplied to the input of the delay element 13, and through it to the control input of the ummator 14, resetting the latter and preparing for work in a new correlation cycle. A signal is applied to the clock input of the switch 2, recording a new sample of the received signal in the corresponding memory element 3.

1264200 41264200 4

После завершения процесса записи новой выборки принимаемого сигнала задним фронтом тактового импульса счетчик 4 переводится в новое состояние. Коммутатор 6 обеспечивает ₅ подключение выхода элементов 3 памяти к первому входу соответствующего блока 7 умножения, к второму входу которого подключены выходы элементов 8 памяти, хранящих выборки опорного ю сигнала-эталона. При этом коммутатор 6 работает таким образом, что всегда обеспечивает поступление в течение цикла корреляции (в процессе рециркуляции) самых старых N выборок 15 принимаемого сигнала (начало принимаемого сигнала) на вход первого блока 7 умножения группы, на второй вход которого поступают первые Ν' выборок опорного сигнала (его нача- 20 ло), а самые новые выборки поступают на первый вход η-го блока 7 умножения группы, на второй вход которого поступают последние Ν’ выборок опорного сигнала (его конец). 25After completing the process of recording a new sample of the received signal by the trailing edge of the clock pulse, the counter 4 is transferred to a new state. The switch 6 provides ₅ connection of the output of the memory elements 3 to the first input of the corresponding multiplication unit 7, to the second input of which the outputs of the memory elements 8 are stored, which store the samples of the reference signal-reference. Moreover, the switch 6 operates in such a way that it always ensures that the oldest N samples of the 15 received signal (the beginning of the received signal) arrive at the input of the first block 7 of the group multiplication, the first Ν 'of the samples arriving at the first input 7 during the correlation cycle (during the recirculation) of the reference signal (its beginning is 20), and the newest samples go to the first input of the ηth block 7 of the group multiplication, to the second input of which the last Ν 'samples of the reference signal (its end) arrive. 25

Группа блоков 7 умножения в течение цикла корреляции (рециркуляции) формирует на своих выходах по Ν' произведений выборок принимаемого 30 и опорного сигналов. Эти произведения поступают на входы сумматора 14, на выходе которого в конце цикла корреляции (рециркуляции) образуется значение функции корреляции все- ₃₅го принимаемого и всего опорного сигналов. После завершения цикла корреляции это значение функции корреляции переносится в регистр 15.The group of multiplication blocks 7 during the correlation (recirculation) cycle generates at its outputs Ν 'the products of samples of the received 30 and the reference signals. These products go to the inputs of the adder 14, at the output of which at the end of the correlation (recirculation) cycle, the value of the correlation function of the entire ₃₅ received and all reference signals is formed. After completion of the correlation cycle, this value of the correlation function is transferred to register 15.

Claims

The invention relates to computing, is intended for the correlation processing of complex signals, and can be used in navigation systems, command and information transmission. The purpose of the invention is to increase speed. The drawing shows a block diagram of a digital correlator. The correlator contains an analog-to-digital converter 1, a second switch 2, a first group of memory elements 3, a third counter 4, a second counter 5, a first switch 6-, a group of multiplication blocks 7, a second group of 8 memory elements, the first counter 9, second element 10 delay, element 11, generator 12 clock pulses, first element 13 delay, adder 14, register 15, one-shot 16, information input 17 of the correlator, output 18 of the corrector The work of the correlator is based on the principle of signal processing in parts, which is to divide the total number of choices the frequency of the received signal (and, accordingly, the reference) on h equal parts and the processing of these parts simultaneously, parallel to time. In this case, the operation of calculating one value of the correlation function, consisting in finding the sum of products of the total number of samples received and reference signals, is replaced by the operation of simultaneously finding the sums of products of individual parts of the total number of samples of the received and reference signals, followed by summing the obtained partial results. In this case, the processing time of the entire signal is determined by the processing time of its separate part and does not depend on the number of parts processed in parallel. The correlator works as follows. From the generator 12 output, the clock pulses are fed to the input of counter 4 and, through element 11, to the input of counter 9. The whole process of calculating one value of the correlation function goes by (N / n) + 1 clock cycles. Sequential change of the states of counters 4 and 9, the address outputs of which are connected to the address inputs of the elements 3 and 8 of the memory, ensures 00 retrieval of information from them, i.e. recirculation of parts of the received and reference signals. Counters 4 and 9 have an equal number of operating states (N - N / n), respectively determining the number of used elements 3 and 8 of the memory. From the output of counter 4, the signal arrives at the first (summation) input of counter 5. This counter has a number of operating states equal to the number of memory elements 3 and indicates the number of the element in which the previous signal sample is stored. Counter 5, together with counter 4, is in fact a counter address of all the elements of the memory 3 used to store the received signal. From the control output of the counter 9 at its NM operation cycle (transfer pulse) the signal arrives at the inputs of the delay element 10 and the one-shot 16. At the next N + 1 clock cycle, the generator 12 clock pulses through the delay element 10 delays the input of the subtraction resolution counter 5. At the same clock cycle, the one-shot 16 sends a signal to the element 11 and blocks (prohibits) the passage of the N + 1 clock pulse to the input of the counter 9. This achieves a shift during the correlation cycle by numbering unit 3 of the memory relative to the numbering elements 8 memory, i.e. the effect of advancing the received signal relative to the reference. During i the time of the correlation cycle, counter 9 successively changes its states from 1st to Nth and again comes to 1st state. Counter 4 during this time changes its state from the initial rth to the Nth, then the 1st and at the end of the correlation cycle, it comes to the r + 1th state. On this N + 1 clock cycle, through the delay element 10, a signal is applied to the control input of register 15, and the calculated value of the correlation function is determined. A signal is fed to the input of the delay element 13, and through it to the control input of the hummer bar 14, resetting the latter and preparing for operation in the new correlation cycle. A signal is sent to the clock input of the 1-1 clock 2, recording a new sample of the received signal into the corresponding memory element 3. After completion of the process of recording a new sample of the received signal by the falling edge of the clock pulse, the counter 4 is transferred to the new state. Switch 6 provides the connection of the output of the memory elements 3 to the first input of the corresponding multiplication unit 7, to the second input of which are connected the outputs of the memory elements 8 that store samples of the reference reference signal. In this case, commutator 6 operates in such a way that it always ensures that the oldest N samples of the received signal (the beginning of the received signal) arrive at the input of the first multiplication unit 7 of the group, at the second input of which the first N the samples of the reference signal (its beginning), and the newest samples arrive at the first input of the n-th block 7 of the intelligent group, the second input of which receives the last N samples of the reference signal (its end). A group of multipliers 7 during a correlation cycle (recirculation) forms, at its outputs, N samples of received and reference signals. These products arrive at the inputs of the adder 14 at the output of which, at the end of the correlation cycle (recirculation), the value of the correlation function of the entire received and the entire reference signal is formed. Upon completion of the correlation cycle, this value of the correlation function is transferred to register 15. Claims of the invention A digital correlator comprising an analog-to-digital converter whose input is the information input of the correlator, the first and second switches, the first and second groups of memory elements, the group multipliers, clock generator, first delay element. an adder, a first counter, an elkmer {t I and a register, and the outputs of the first switch are connected to the first inputs of the respective multiplicators of the group, the first output of the controlled generator is connected to the register recording input, characterized in that, in order to improve speed, a second delay element, one-shot, second and third counter, the output of the analog-digital converter connecting with the information input of the second switch, the control of which is combined with the input of the first switch of the same name Pa and connected to the output of the second counter, the outputs of the second switch are connected to the information inputs of the corresponding memory elements of the first group, the address inputs of which are connected to the information output of the third counter, the counting input of which is combined with the first input of the And element and connected to the output of the clock generator, output the transfer of the third counter is connected to the input of the summation permission of the second counter, the input of which the permission of the subtraction is combined with the clock input of the second switch and through the first The delay element is with the resolution addition input of the adder, and through the second delay element is combined with the one-shot input and connected to the transfer output of the first counter, the one-shot output is connected to the second input of the And element, the output of which is connected with the first input of the first counter, the information output of the first counter is connected to the address the inputs of the memory elements of the second group, the outputs of which are connected to the second inputs of the corresponding multiplication units of the group, the outputs of which are connected to the corresponding information the inputs of the adder, the output of which is connected to the information input of the register, the output of which is the output of the correlator.