RU1815652C - Correlation device - Google Patents

Abstract

The invention relates to specialized information retrieval devices and is used to determine the delay time between random signals. The purpose of the invention is to simplify the device. The device contains a shift register 1, a group of counters 2, a group of elements AND 3, a group of elements EXCLUSIVE OR 4, an element NOT 5, a delay code generating unit 6, a synchronizer 7, a trigger 8, a group of shift registers 9, an N-channel multiplexer 10, a switch 11 , element OR 12, element AND 13, delay element 14 and key 15. 2 ill.

Description

i

The invention relates to specialized digital information retrieval devices and is used to determine the delay time between random signals by calculating the sign correlation function.

The purpose of the invention is to simplify the device while maintaining the same accuracy,

In FIG. 1 shows a functional diagram of an inventive device; figure 2 - exchange charts illustrating the operation of the device.

Functional diagram (Fig. 1) contains a shift register 1, a group of counters 2-1-2-N, a group of elements AND 3-1-3-N, a group of elements EXCLUSIVE OR 4-1-4-N. element NOT 5, block b generating the delay code, synchronizer 7. trigger 8, a group of registers 9-14HN-1) shift, N-channel multiplexer 10, switch 11, element OR 12, element 13, delay element 14 and multi-bit key 15.

The first inputs of the elements EXCLUSIVE OR 4-1-4-N are connected to the output of the element NOT 5, the input of which is the information input X (tr) of the device, the second inputs of the elements EXCLUSIVE OR 4-t-4-N are connected to the corresponding bit outputs of the register 1 pass, the first input of the element AND AND AND 12 is connected to the zeroing input 1 of block b and is the zeroing input P T, device, the output of the element OR 12 is connected to zeroing inputs of the counters 2-1-2-N, outputs AND 3-1-3-N elements are connected to the counting inputs of the corresponding 2-1-2-M counters. CLAIMING OR 4-1-4-N are connected to the first inputs of AND 3-1-3-M elements, the second inputs of which are connected to the output of the synchronizer 7, the trigger input 1 of which is the device trigger input CO, the clock input 2 of the synchronizer 7 is connected to the clock input of the shift register 1, the clock input of which is connected to the output of the switch 11. The first information input of which serves as the first clock input C K1 of the device, the second information input of the switch 11 serves as the second clock input CLK2 of the device, the clock inputs of the registers 9-1-9- {N -1) shear combined and by connected to the second clock input CLK2 of the device, the input X (t) of the reference signal of which is the information input of the shift register 9-1, the penultimate (in the direction of the shift) bit output is connected to the first information input of the multiplexer 10, the penultimate bit output of the register 9- 2 shifts connected to the second

information input of the multiplexer 10, the penultimate bit output of the shift register 9- (N-1) is connected to the (M-1) -th information input of the multiplexer 10, the output of the shift register 9-1 is connected to the information input of the shift register 9-2 and even rule: the output of the shift register 9-i is connected to the information input of the shift register 9- {i + 1) shift (I 1, N-1) the zero information input of the multiplexer 10 is connected to the input X (t) of the reference signal of the device, the output of the multiplexer 10 is connected .denine with register information input

1 shift, the control input of the switch 11 is combined with the first input of the element And 13 and connected to the direct output of the trigger 8, the clock input of which is combined with the input 3 of the shutdown of the synchronizer and connected to the output 3 of the start of operation of block b, the output

2, the end of which is connected to the second input of the AND element 13. The output of which is connected to the second input of the OR element 12. The inverse output of trigger 8 is connected via the delay element 14 to the enable input of key 15. The multi-bit information input of which is combined with the address input of multiplexer 10 and is connected to the information output of block 6, the information inputs of which are connected to the overflow outputs of the corresponding counters 2-1-2-M, the zeroing inputs of the shift register 1 and trigger 8 are connected to the zeroing input RST of the device. The information output of which is the multi-bit output of the key 15.

timing charts (figure 2) contain:. ; ;. . ,:. ::

pulses RST zeroing the device (figa),

the pulse WITH the launch of the device (figb),

logical levels at the output 3 of the beginning of the operation of block 6 (pigv).

clock pulses at the output of the synchronizer 7 (Fig.2g),

 logical levels on the direct output of trigger 8 (fig.2d),

logical levels at the enable input of the key 15 (Fig.2E),

the current code ni at the information output of block 6, at the stage of rough estimation of u-1 and at the stage of accurate evaluation of P2-1, respectively (Fig.2g).

The principle of operation of the device (Fig. 1) will abate in the following.

Prior to the analysis, by applying a nulling pulse to: stroke P5T (Fig. 2a), the device is set to its initial state. Advance X (t) i and delayed by time X (t-t) signals are fed to the corresponding inputs of the device, in which shift register 1 and a group of shift registers 9 are continuously clocked. In this case, the multiplexer 10 switches the signal X (t) directly from the input of the device to the input of register 1, which is accompanied by the appearance of delayed copies of X (t) on the digital outputs of register 1. Moreover, the multiplexer 11 of the initial state supplies to the clock input of register 1 a sequence of pulses CLK1 with a repetition period, where T2 is the repetition period of pulses in the sequence CLK2.

With the arrival of the CO control input (Fig. 26), the trigger pulse device begins the first stage of the calculation cycle — the stage of preliminary rough estimation of the position of the central inter-correlation peak (CVC) with time resolution in TL. In response to the trigger pulse, synchronizer 7 generates a strobe signal allowing recording the results of bitwise matches with the output of the elements EXCLUSIVE OR group 4 to the counters of group 2, which is provided by applying clock pulses to the combined inputs of the elements AND group 3 (Fig. 2d). When one of the counters of group 2 overflows, block 6 generates a signal for the end of the stage (Fig. 2c), which (signal) is supplied to the corresponding input of synchronizer 7 (from output 3 of block 6 to input 3 of synchronizer 7). in this connection, the arrival of clock pulses to the combined inputs of the And elements of group 3 is interrupted and trigger 8 is set to a single state (Fig. 2e). Besides. block b, which performs, among others, the function of the overflow channel number encoder, determines the channel number of the overflowed counter and sets the corresponding code ni-1 at the address input of multiplexer 10 (Fig. 2g). At the same time, at the output 2 of the end of operation of block 6, a high logic level is set, resetting the counters of group 2. At this point, the rough estimation stage ends, the result of which is a delay code n i. obtained by time resolution in TL Then, the trigger 8, which has become in a single state, puts the switch 11 in a position that allows CLK2 pulses with a period of T2 to pass to the clock input of register 1. T.O. register 1 is put into the multi-delay line operation mode already with a delay discrete in T2.

The next step is to evaluate the position of the high-resolution digital color PCB, i.e. with a decree in T2. The signal X (t) is delayed in the chain of registers of group 9. s

one of the bit outputs of which it is switched to the information input of register 1. Moreover, the signal is taken from the output of register 9-i. if at the stage

a rough estimate, counter 2- (M 1) was overflowed. The foregoing makes it possible at the present stage to use register 1, elements of group 3. 4 and counters of group 2 for correlation analysis, no longer in the entire range of permissible delays, but only in the circle of the previously roughly calculated position of the CEHEC. When one of the counters of group 2 is overflowed, the counter leading to the counters is interrupted, and also set to zero

5 trigger 8 (fig.2d). The latter leads to the appearance of a delay in time of the unlocking high logic level (Fig. 2e) at the enable input of key 15. which transmits to the component output

0 P2-1 delay code.

In the rough estimation step, the position of the DECC in the range from 0 to (N-1) Ti is calculated. In the next step with a higher resolution, the analysis is carried out in the range from

5 ((m-1) Ti -T1 / 2) to ((gm-1) T1 + Ti / 2), moreover 2.N. It is easy to see that the bandwidth is Ti, i.e. the rough estimate discrete equal to T1 is divided into a number of intervals of width T2. In turn, the delay line synthesized from the registers of group 9 should provide a delay of sigTi

5

0

5

0

5

X. (g) at the time of ((rn-1) Ti - condition Ti

TD D

i

To ensure this condition, register 9-1 should contain ku-41 bits, and each of registers 9-2-9- (N-1) in Ti / T2 bits. The number of bits of the register 1. necessary to cover the range

a width of Ti delivers N - +1. Besides

One of the necessary requirements is the connection to the information inputs of the multiplexer 10 of the last but the last (in the direction of shift) bits of the registers of group 9, the last bit outputs of which are connected to the information inputs of the next in the chain of registers.

The desired delay time g is calculated by the formula

g (m-1) Ti-b. + (p2-1) T2

where P2 is the number of the channel that has overflowed at the stage of accurate estimation. The value code is set to the multi-bit output of the device (Fig. 2g) at the end of the second analysis step. As for the code of the quantity u-1, it is formed by block b in

at the end of the first stage of analysis and throughout the second stage it is stored in its memory with output to the address bus of multiplexer 10. To store the indicated codes - components of code d - buffer registers connected to the address and output buses of the device can be used. Information can be recorded, for example, by a strobe pulse from the output of element And 13 to a register connected to the address bus and from output 2 of block 6 to a register connected to the output bus of the device.

The delay element 14 is necessary to shift the release time of the key 15 by the time during which the block 6 searches for an overflow channel. Therefore, the delay introduced by element 14 depends on the speed of block 6 and can be set as t, s S N g (T is the repetition period of clock pulses of the internal clock generator of block 6),,

As a multi-bit key 15, either multi-channel switches of type 176 CT1 and 561 CTZ, or a group of 2I elements, one of whose inputs are combined and constitute the key enable input, and other inputs serve as information inputs, can be used.

The technical and economic efficiency of the device compared to the prototype consists in reducing the hardware volume by eliminating one of the two multichannel correlation blocks, which are the most capacious nodes of the device (in the prototype device, the excluded block is shown as block 10).

Claims (1)

SUMMARY OF THE INVENTION A correlation device comprising a shift register, a group of counters, a group of AND elements, a group of EXCLUSIVE OR elements, an NOT element, a group of shift registers, an OR element, a synchronizer, an AND element, and a delay code generator, the first inputs of the EXCLUSIVE OR groups are connected to the output of the element is NOT, the input of which is the first information input of the device, the second inputs of the elements are EXCLUSIVE OR groups are connected to the corresponding bit outputs of the shift register, the first input of the element is OR It is connected to the zeroing input of the delay code generation unit and is the zeroing input of the device, outputs elements AND groups are connected to the counting inputs of the corresponding counters of the group, the outputs of the elements EXCLUSIVE OR groups are connected to the first inputs elements And groups, the second inputs of which are connected to the output of the synchronizer, the start input of which is the output of the device start, the clock inputs of the group shift registers are combined and connected to the first clock input of the device, characterized in that, for simplicity, a multiplexer, a switch are inserted into it , trigger, delay element and key, the output of which is the information output of the device, the second information input of which is the information input of the first group shift register, (N-1) -th bit output j-ro p the group shift register is connected to the multiplexer information input of the same name (i 1.N-1: N is the number of multiplexer channels), the output of the group shift register j-ro (j 1.N-2) is connected to the information input (j + 1) -ro group shift register, null the information input of the multiplexer is connected to the input of the reference signal of the device, the output of the multiplexer is connected to the information input of the shift register, the clock input of which is connected to the output switch, the first and second information inputs of which are respectively the first and second clock inputs of the device, the control input of the switch is combined with the first input of the And element and connected to the direct output of the trigger, the clock input of which is combined with the stop input of the synchronizer and connected to the output of the start of work of the delay code generation unit, the end of work output which is connected to the second input of the AND element, the output of which is connected to the second input of the AND element, the output of which is connected to the second input of the OR element, the inverse trigger output through the element the delay is connected to the control input of the key, the information input of which is combined with the address input of the multiplexer and connected to the information output of the delay code generation unit, the information inputs of which are connected to the overflow outputs of the corresponding counters, groups that reset the inputs of the shift register and trigger are connected to the reset input device output element OR connected to resetting inputs of group counters.