SU1413643A1 - Correlator time delay discriminator - Google Patents

Description

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The invention relates to computing technology and can be used in specialized devices for processing M-sequences, for example, S in navigation receivers, 5 radio astronomy devices, digital detectors and digital.

The purpose of the invention is to improve the accuracy and enhance the functionality by determining the instantaneous delay: |; ki when changing the relative delay with a speed comparable to the speed of the discriminator.

The drawing shows the flow chart of the discriminator.

The discriminator contains the first 1 and second 2 shift registers, the elements EXCLUSIVE OR NOT 3.1-Z.p, the element EXCLUSIVE OR 4 elements 5-8, the multivariate element AND 9, the element OR 10, the first 11 and the second 12 triggers the first 13 and second 14 counters and shaper 15 and shulsa.

The discriminator works as follows.

The first input X (t) is supplied with an M-sequence, which is ahead of a similar sequence at the input Y (t). The time instant, which is a relative delay, is determined by the moment when the control impulse discriminator starts. , on the leading edge of which the counter 14 is zeroed and the trigger 12 is transferred to the one state, when the latter overturns the second input of the And 5 element, a high level is established and the trace bits from the y (t) input are sequentially entered into the register 2, the same most about It also proceeds in register 1 after the feed to its clock input of clock pulses from the output of the element 6, at the same time the counter 13 maintains even clock pulses fed to the register 1 register input, used to record the N bits of the input signal 25

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On the other hand, after the occurrence of the N-ro sync pulse, overflow of the counter 13 appears a positive voltage drop, which returns the trigger 12 to the zero state and accordingly stops the access and shift of information JI in register 1, translating it thus in storage mode. Simultaneously at the direct output of the trigger. 1 sets the high level to allow

14 clock pulses go to the counting input of the counter, which at this stage act as counting pulses. The counter 14 begins to work out the value of the instantaneous relative delay. Since the trigger 12 after the Nro sync pulse returned to its original state, the input of the sequential input of register 2 information instead of the M-sequence symbols from the output, Y (t) begins to receive through the elements 7 and OR 10 two-fold modulo a pseudo-random sequence, y7ke recorded in register 2, which is continuously clocked.

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Thus, register 2 is matched for some time by feedback, allowing it to be treated as a generator of the M-sequence, with {: a polynomial defined as a fragment of a pseudo-random sequence in N ticks. The consequence of this is the repetition at the bit outputs of register 2 of that fragment of the M sequence, which was previously recorded in register 2. Moreover, the time required for the synthesized generator to repeat the desired fragment along the entire length of the register is counted by counter 14, and the end of the reference interval, i.e. . stopping testing the desired time, arrives when the character identification of characters recorded and modeled by the M-sequence is bit-wise over the length of N, a voltage jump at the output of the AND 9 element is converted by the pulse shaper 15 into a pulse, the duration of which is sufficient to zero registers 1 and 2, the counter 13 and the zeroing of the trigger 12, as a result of which the clock pulses are stopped at the counting input of the counter 14, and the code defining the desired time is fixed at its bit outputs. SAP-governmental relative delay which is zeroed when the next trigger pulse.

Claims (1)

Invention Formula The correlation discriminator of the delay time, which contains the first and second shift registers, the group of elements EXCLUSIVE OR NOT, the four elements AND, and the information input of the first shift register is 3,113,634. the first information input of the first counter of the first register of the shift register is the clock element AND connected to the first input of the discriminator, the bit output of the element OR, the output of which is the moves of the first and second shift registers are connected to the information input of the second connected respectively to the first shift register, the second inputs and the second inputs of the corresponding element OR are connected to the output of the three elements EXCLUSIVE OR NONE groups, of the second element AND, the first input of which is characterized by the fact that -Q go is connected to the inverse output, in order to increase the accuracy, it has a loose trigger, the installation input is entered into the EXCLUSIVE OR element, which is connected to the installation input ment OR, the multi-input element I, in O of the second counter, is two triggers, two counters, the input formed to start the discriminator, the pulse counter, and the outputs are ele- The second input of the counter is connected to the EXCLUSIVE IL-NOT groups connected to the output of the fourth element I, transmitted to the corresponding inputs, the input of which is connected to the direct 1 input input and the output of the first trigger, the second input of which is connected to the input of the input - the fourth element And is connected to the pulse of the pulse, the output of which is connected -. discriminator input, the output with the installation inputs in the first O and the overflow of the first counter of the second shift register, the first yen with the installation input in the second counter, the first trigger, the first trigger and the input of the first input of the first element I is the second first trigger, the second input of the third information input discriminates jc ° element And is connected to the elec- tor output, the second input of the first element of the EXCLUSIVE OR element, the first and second And is connected to the forward output of the second swarm whose inputs are connected to the corresponding trigger the first input of the second electrical outputs of the starposaos of the size I, the second input of which is connected to the second shift register, is discharged with the clock input of the second regional outputs of the second counter are the shift offset and the output of the second element of the delay code discriminator, that And is connected to the clock input per