SU819968A1 - Repetition rate scaler with fractional devision coefficient - Google Patents

Description

(54) THE DIVIDER OF THE FREQUENCY RATING OF PULSES WITH A FRACTURAL DIVISION COEFFICIENT

is chosen equal to K 4, and the number of bits of the register 2 n 5.

The input bus 8 of the device receives a sequence of pulses with a period of following T, which must be divided into 4-. Sigal from the output of counter 1 is fed to the clock input of register 2, which should work, for example, on a ring circuit, or on any other ensuring the continuity of its work. For definiteness, we assume that the trigger changes its state if there is a drop from one to zero on the C input.

in principle, the device is operational with any other algorithm of the trigger on the C-output. Therefore, the output of the first register bit 2 in Vits after the cutoff of the first pulse (Fig. 26) and extends to the cutoff of the second pulse. This output is depicted in FIG. 2c. This signal is fed to the first control input of element 3. The input from element 3 receives a signal from the output of counter 1 (Fig. 26). The signal entering the strobe of the first output of the register (Fig. 2c) in element 3 is delayed by an equal time and arrives at the output bus 9 (Fig. 2n).

The signal from the output of the second bit of the register 2 is fed to the second control input of the element 3 and now the pulse caught in the strobe of the second bit of the register is delayed in the element 3 for the time T and goes to the output bus 9.

At the same time, the strobe of the second bit of register 2 is fed to the first input of element 4 and from its output to the second input of element 5, the first input of which receives a signal from the output of counter 1 (Fig. 26). At the output of element 5, a pulse is generated that acts on the R-input of the trigger 6 and sets it in such a position that a single level is formed at its output, which continues until the pulse 13 is cut (Fig. 2a) of the input sequence applied to the C input trigger 6 sets it to zero. It should be borne in mind that the pulse preceding the pulse 13 does not cause a change in the state of flip-flop 6, since the duration of the cutoff of this pulse is overlapped by the action of zero potential at the R input of flip-flop 6 from the pulse 12. This overlap always takes place, since pulse 12 is formed from this pulse, but is delayed during the formation in register 2, element 4, element 5. The second input of element 7 receives a signal (Fig. 2h) from the output of element 5, therefore a signal is formed at the output of element 7 (Fig. 2k ) providing overlap pulse time 13. This signal is fed to the installation input of the counter

1, whereby the pulse 13 is not counted by the counter 1, and the next pulse 14 at the output of the counter 1 is passed through five periods of the input sequence (Fig. 2a).

This pulse will go to the input of the element 3, the third control input of which will receive a signal from the output of the third bit of register 2 (Fig. 2e). In element 3, pulse 14 is delayed by a time of 4-T, and pulse 16 by counter 1 is not counted again and the next pulse 17 is passed through five periods of the input sequence.

In this case, the fifth control input of the element 3 will receive a signal from the output of the fifth register bit (Fig. 2g) pulse 17 arrives at the output bus 9 without delay in the element 3. Then the cycle repeats.

Thus element 3 has a ". 5 control inputs, and element 4 has 0 and 2 inputs (second and fourth).

Obviously, between any-pulses of the output sequence on bus 9, the time interval is 4- | -T.

This device provides the division of the input sequence by any non-integer coefficient and has a high speed while simplifying its implementation.

Claims (2)

Invention Formula A pulse frequency divider with a fractional division factor, containing a pulse counter, the counting input of which is connected to the input bus, the delay element, the trigger and the And elements, the first input of the first of which is connected to the output of the pulse counter, and the output to the R input of the trigger and the first the input of the second element AND, characterized in that (J in order to increase the speed of the device while simplifying it simultaneously, the OR element and the register are entered in it, the first group of outputs of which is connected to the control elements of the delay element, the second group of outputs - with the corresponding inputs of the OR element, and the input - with the input of the delay element and the output of the pulse counter, the counting input of which is connected to the C input of the trigger, and the setup input - with the output of the second element And, the second input of which is connected to the output of the trigger. Sources of information taken into account in the examination. 1. USSR author's certificate No. 425358, cl. H 03 K 23/00, 03/01/72. . e 2. USSR author's certificate No. 572933, cl. H 03 K 23/00, 03/15/76.