SU1410057A1 - Crrelation device for measuring delay - Google Patents

Abstract

The invention relates to the field of specialized digital computing equipment and can be used to measure the geometric delay in a superlong-base radio interferometer operating with an object emitting pseudo-random signals. The purpose of the invention, the improvement of accuracy, is achieved by using to process the entire accumulated array of information. The device contains two shift registers 1,2, two groups of elements And 3.4, a comparison block 5, a glint of adjustable delay 6, a synchronization block 7, three counters 8, 10, 11, a decoder 9, an RS flip-flop 13, two elements And 14 , 15, element OR 16 and display unit 12. 2 Il. with s

Description

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The invention relates to the field of specialized digital computing equipment and can be used to measure the geometric delay in a radio interferometer with a super-long baza working with an object that radiates pseudo-random signals.

The purpose of the invention is to improve accuracy.

FIG. 1 shows a block diagram of the device in FIG. 2 is a block synchronization diagram.

The correlation device for determining the delay contains the first 1 and second 2 shift registers, the first 3 and second 4 groups of elements AND, the comparison unit 5, the adjustable delay unit 6, the synchronization unit 7, the second counter 8, the decoder 9, the first counter 10, the third counter 11, the display unit 12, the RS-trigger 13, the first 14 and second 15 elements And the element OR 16.

FIG. 2 shows a block diagram of a synchronization unit 7 consisting of the third element OR 17, the second element AND 18, the delay element 19, the third 20 and the second 21 pulse shapers, the counting trigger 22, the second counter 23, the RS flip-flop 24, the third counter

25, first pulse former

26, the second 27 and 28 elements OR, the first counter 29, the clock pulse generator 30 and the first element AND 31.

The device works as follows.

On the information input of the register of the register 1, the first array X (t) is retransmitted to the processing point. The input of the block of adjustable delay 6 receives the array recorded at this point y (t). The information inputs of the third counter 11 and the delay unit 6 are fed from the external control device by the code of the calculated value of the current geometric delay.

When the start signal appears, the first counter 10 is reset, the input information is copied to the outputs of the third counter 11, the sync pulses are generated at the second output of the synchronization unit 7, N digits from the X (t) array and from the shifted () value are written to the shift registers 1 and 2 | array), followed by

an RS-trigger is set 13. The information stored in shift register 2 is shifted by a certain number of cycles, which determines the outcome

of the maximum possible error between the compensated and calculated geometric delay. If at the same time the codes are not in the moves of the block compare 5

match, which can occur if there is an error in the relayed array, at the transfer output of the second counter 8 a pulse is formed, which is fixed by the first counter

from 10. This results in a shift of pulses in shift register 2 in the opposite direction for n cycles. Low logic level arising on the corresponding output decrypt

 Ratio 9 locks the corresponding AND elements of the first 3 and second 4 groups, excluding the comparison of the m bits of shift registers 1 and 2. The number m should be determined from the condition where K5 is the maximum possible number of consecutive errors. If the subsequent shift of information in shift register 2 in the forward direction doesn’t result in coincidence of codes again, then the group of bits switched by the following elements And first 3 and second 4 groups of elements And, etc. will be excluded from the arrays. When the codes at the output of the comparison block S coincide, a pulse appears,

5 resetting NC-trigger 13. The code observed at the output of the display unit. 12 corresponds to the value of the compensated geometric delay. Geometric

0

delay for other times.

Claims (1)

Invention Formula A correlation device for determining the delay, containing the first shift register, whose information input is the first information input of the device, the second shift register, two groups of And elements, the decoder and two counters, the outputs of the first and second shift registers being connected to the first the inputs of the corresponding elements And, respectively, the first and second groups of elements And, in the mountain inputs of which are connected to the corresponding outputs of the decoder, the information input of which is connected to the output of the first counter, different in order to increase accuracy, a comparison block, a short-cut trigger, two AND elements, a WIT element, a third counter, a display block, a synchronization block and an adjustable delay block, whose information input is the second information input of the device, are entered into it; the output is connected to the information input of the second shift register, the output of the elements And the first and second groups of elements AND are connected respectively to the first and second information inputs of the comparison unit, the output of which is connected to the reset input of the RS flip-flop, inverse the stroke of which is connected to the display enable input of the display unit, and the direct output to the first input of the first element AND whose output is connected to the first input of the OR element and the first input of the second element AND whose output is connected to the counting input of the second counter whose transfer output is connected with the counting input of the first counter and with the input of the setting of the synchronous block mode the output of the SHS element is connected to the counting input of the third counter, the outputs of which are connected to the information inputs of the display unit, the first output of the synchronization unit is connected to the shift control input of the second shift register and the second input of the second And element, the second output of the synchronization unit is connected to the clock inputs of the adjustable block delays of the second shift register, as well as with the second input of the first element I, the third output of the synchronization block is connected to the clock input of the first shift register, the fourth output of the block The synchronization is connected to the setup input of the RS flip-flop, the fifth output of the synchronization unit is connected to the second input of the OR element and the reset input of the second counter, the sixth output of the synchronization unit is connected to the counting enable input of the third counter, the seventh output of the synchronization unit counter.