SU849474A1

SU849474A1 - Pulse discriminator

Info

Publication number: SU849474A1
Application number: SU792769210A
Authority: SU
Inventors: Игорь Михайлович Соколов
Original assignee: Предприятие П/Я А-7162
Priority date: 1979-05-23
Filing date: 1979-05-23
Publication date: 1981-07-23

Description

(54) СЕЛЕКТОР ИМПУЛЬСОВ(54) PULSE SELECTOR

1one

Изобретение относитс к импульсной технике.The invention relates to a pulse technique.

Известен селектор импульсов, содержащий два регистра сдвига, блок управлени и ввода, логические элементы И, генератор опорного сигнала A pulse selector is known, comprising two shift registers, a control and input unit, logic gates, and a reference signal generator.

Данный селектор импульсов не обеспечивает достаточной точности.This pulse selector does not provide sufficient accuracy.

Наиболее близким по технической сущности к предлагаемому вл етс селектор , содержащий входной элемент И, один вход которого соединен с входной шиной, второй вход соединен с первым входом переключател и первым выходом блока управлени , а выход - с первым входом блока пам ти и первым входом элемента И, второй вход которого соединен с выходом блока пам ти, а третий вход - с вторым выходом блока управлени , входы разр дов блока пам ти соединены с соответствующими выхЬдами блока управлени , а второй и третий входы блока пам ти соединены с выходами переключател , второйThe closest in technical essence to the present invention is a selector comprising an input element I, one input of which is connected to the input bus, a second input connected to the first input of the switch and the first output of the control unit, and the output to the first input of the memory unit and the first input of the element And, the second input of which is connected to the output of the memory unit, and the third input to the second output of the control unit, the inputs of the bits of the memory unit are connected to the corresponding outputs of the control unit, and the second and third inputs of the memory unit are connected to moves the switch, the second

вход которого подключен к Третьему выходу блока управлени , четвертый выход которого соединен с первым входом выходного элемента И, а вход блока управлени соединен с шиной сигнала сброса 2.the input of which is connected to the Third output of the control unit, the fourth output of which is connected to the first input of the output element AND, and the input of the control unit is connected to the reset signal bus 2.

Однако такое устройство обладает недостаточной точностью селектировани .However, such a device has insufficient selection accuracy.

Цель изобретени - повышение точ10 ности селектировани отдельных импульсов .The purpose of the invention is to improve the accuracy of selection of individual pulses.

Поставленна цель достигаетс тем, что в селектор, содержащий входной ,5 лементИ,од1т вход которого соединен С . входной шиной,второй вход соединен с первым входон переключател и первым выходом блока управлени ,а выход - с ервым входом блока пам ти и первым входом элемента И,второй вход которого The goal is achieved by the fact that a selector containing an input, 5 lements, one input of which is connected to C. the input bus, the second input is connected to the first input of the switch and the first output of the control unit, and the output is connected to the first input of the memory unit and the first input of the And element, the second input of which

30 соединен с выходом блока пам ти, а третий вход - с вторым выходом блока травлени , входы разр дов блока пам jГИ соединены с соответствующими вы-30 is connected to the output of the memory unit, and the third input is connected to the second output of the etching unit, the inputs of the bits of the jIG memory unit are connected to the corresponding outputs

ходами блока управлени , а второй и третий входы блока пам ти соединены с выходами переключател , второй вход которого подключен к третьему выходу блока управлени , четвертый выход которого соединен с первым входом выходного элемента И, а вход блока управлени соединен с шиной сигнала сброса, введены блок сравнени , сумматор рассогласовани и элемент задержки, первый вход которого соединен с входом сумматора рассогласовани и третьим выходом блока управлени , второй вход сумматора -рассогласовани подключен к выходу входного элемента И, а выходы сумматора рассогласовани соединены соответственно со вторыми входами выходного элемента И и элемента задержки , третий вход которого подключен к i шине сигнала запуска, а выход - ко вто рому входу блока управлени ,п тый и шестой выходы которого соединены с первым и вторым входами блока сравнени , третий вход которого Подключен к выходу элемента И, а четвертый входк шине сигнала,кода, блок сравнени со держит счетчик, входы которого сое динейы с первым и третьим входами блока сравнени , буферный регистр, входы которого соединены со вторым и четвер-зо the control unit, and the second and third inputs of the memory unit are connected to the switch outputs, the second input of which is connected to the third output of the control unit, the fourth output of which is connected to the first input of the output element AND, and the input of the control unit is connected to the reset signal bus; comparison, the adder mismatch and the delay element, the first input of which is connected to the input of the adder mismatch and the third output of the control unit, the second input of the adder-mismatch connected to the output of the input element And, and the outputs of the error adder are connected respectively to the second inputs of the output element I and the delay element, the third input of which is connected to the i bus of the trigger signal, and the output to the second input of the control unit, the fifth and sixth outputs of which are connected to the first and second inputs comparison block, the third input of which is connected to the output of the element I, and the fourth input of the signal bus, code, the comparison block contains a counter whose inputs are connected to the first and third inputs of the comparison block, the buffer register whose inputs us with second and fourth

тым входами блока сравнени , и сумматор по модулю два, входы которого подключены к выходам упом нутых счетчика и буферного регистра.The two inputs of the comparison unit, and a modulo-two adder, the inputs of which are connected to the outputs of said counter and buffer register.

На чертеже изображена структурна 35 электрическа схема селектора.The drawing shows a structural 35 electrical selector circuit.

Описываемый селектор содержит блок 1 пам ти, элементы И 2-4, переключатель 5, блок 6 управлени ,состо щий из счетчика 7, дешифратора 8, 40 триггеров 9,10, элементов И 11 и 12, генератора 13, блока 14 сравнени , состо щего из счетчика 15, сумматора 16 по модулю ..два, буферного регистра 17, сумматор 18 рассогласовани , элемент 45 19 задержки. Входной сигнал подан на шину 20, на шины 21, 22 и 23 поданы сигналы сброса, кода и запуска. Выходные сигналы снимаютс с выходов 24 и 25.50The described selector contains memory block 1, elements AND 2-4, switch 5, control block 6 consisting of counter 7, decoder 8, 40 flip-flops 9.10, elements 11 and 12, generator 13, comparison block 14, from the counter 15, the adder 16 modulo .. two, the buffer register 17, the adder 18 mismatch, the element 45 19 delay. The input signal is fed to the bus 20, on the bus 21, 22 and 23 signals of reset, code and start are given. The output signals are taken from outputs 24 and 25.50

Селектор работает следующим образом .The selector works as follows.

Под действием внешнего импульса сброса, подаваемого на шину 2I, счетчики 7 и 15 устанавливаютс в нулевое 55 1исходное состо ние, а в буферный регистр 17 с шины 22 вводитс код, опре (Дел ющий длительность селектируемыхUnder the action of an external reset pulse applied to the bus 2I, the counters 7 and 15 are set to zero in the initial state, and a code is entered into the buffer register 17 from the bus 22, which defines (Dividing the length of the selected

импульсов, При этом, под действием возбужденной нулевой шины дешифратора 8 срабатьшают тоиггепы 9 и 10. Триггер 9 отключает элемент И if, а триггер 10 обеспечивает установку переключател 5 в положение Запись, счетчика 7 и сумматора 18 рассогласований в режим сложени и обеспечивает отключение элементов И I2 и 3 на врем , равное первой половине заданного строба. Внешний импульс Запуск , поступающий на шину 23, пройд через элемент 19 задержки обеспечивает срабатывание триггера 9, который подключает элемент И II, при этом импульсы поступают на счетный вход счетчика 7, который вместе с дешифратором 8 последовательно формирует все адреса на адресных шинах блока 1 , поimpulses, however, under the action of the excited zero bus of the decoder 8, trigger 9 and 10 trigger signals. Trigger 9 disables the AND element, and trigger 10 ensures that switch 5 is set to Record, counter 7 and adder 18 mismatches in add mode, and ensures disconnection of AND elements I2 and 3 for a time equal to the first half of the specified gate. External impulse Starting on bus 23, passing through delay element 19 provides trigger for trigger 9, which connects element II, while pulses arrive at the counting input of counter 7, which together with decoder 8 sequentially generates all addresses on address buses of block 1, by

Claims

trigger 10, which sets the switch 5 to the read position, the counter 7 and the error accumulator 18 - into the subtraction mode and provides connection of the elements 12 and 3 for the time of the second half of the specified strobe, but in the presence of pulses at the output of the element And P. Counter 7 generates successively all the addresses relative to the middle of the strobe on the address buses of the storage device 1, by which the information recorded during the first half of the strobe is selected from it. At the same time, in the error accumulator 18, the number of quantized pulses coinciding in time with the useful signal in the period of existence of the second half of the strobe is subtracted from the sum of quantized pulses that coincide in time with the useful signal during the existence of the first half of the gate. The result of the calculation (i.e., the mismatch) during the existence of the last address is entered into delay element 19 (with memory therein) and outputted at output 24 of the pulse selector. which records information received from bus 20 through element 4 during the time that the first half of the gate exists. At the same time, the C5 matrix 18 mismatch counts (more precisely, adds up) the number of quantized pulses that coincide with the lifetime of the useful signal. The last address in the first half of the strobe, formed at the output of the decoder 8, provides simultaneously with the counter 15 counts pairs of equidistant pulses, each of which is located in opposite parts of the temporal position of the middle of the strobe, which come from the output of the And 3 element. the coincidence of the code generated at the output of the counter 5 with the code recorded in the buffer register 17, at the output 25 of the pulse selector, forms a pulse indicating the presence of a pulse of a given duration in the middle of the strobe. In this case, the output 24 forms a code corresponding to zero or minimum mismatch, which ensures the setting of the average delay in element 2. In the absence of a pulse at the output 25, but in the presence of a pulse of a given length in the gate, the temporal location of which is offset from the middle gate strobe the side of the first (second) half gate, at the output 24, a positive (negative) mismatch code is generated, which ensures the gate is shifted in the appropriate direction by decreasing (increasing) supports in the element 19. The last address during the existence of the second half of the strobe, formed at the output of the decoder 8, ensures that the device is reset. acts as an external reset). After the next pulse arrives. The start-up cycle is repeated. Claims. 1. Pulse selector containing input element I, one input of which is connected to the input bus, second input connected to the first switch input, l and the first output of the control unit and to the first input of the memory block and the first input of the element I whose input connected to the output of the memory unit, and the third input to the second output of the control unit, the inputs of the bits of the memory unit are connected to the corresponding outputs of the control unit, and the second and third inputs of the memory unit are connected to the outputs of the switch, the second input of which is connected to the third output of the control unit, the fourth output of which is connected to the first input of the output element-I, and the input of the control unit is connected to the reset signal bus, characterized in that, in order to improve the selection accuracy of individual Shch1pulses, a comparison unit, a mismatch and the delay element, the first input of which is connected to the input of the mismatch adder i by the third output of the control unit, the second input of the sum, the error tolerant is connected to the output of the input element I, and the summers of the adder mismatch The vanes are connected respectively to the second inputs of the output element I and the delay element, the third input of which is connected to the trigger bus, and vpsod to the second input of the control unit, the fifth and sixth outputs of which are connected to the first and second inputs of the comparator, the third input of which is connected to the output of the element And, and the fourth input - to the signal signal bus.

2. The selector according to claim 1, which is distinguished by the fact that the comparison unit contains a counter, the inputs of which are connected to the first and third inputs of the comparison location, a buffer register, the inputs of which are connected to the second and fourth inputs of the comparison block, and a modulo two The inputs of which are connected to the outputs of the above-mentioned counter and buffer register. Sources of information,: taken into account in the examination I. US patent. No. 3550017, cl. 340174, dated 12.22.70. 2 "USSR Author's Certificate in Application No. 2539870 / 18-21, cl. H 03 K 5/18 dated 11/01/77.