SU1352535A1 - Self-monitoring shifting device - Google Patents

Abstract

The invention relates to computing and can be used, for example, in constructing delay lines for digital filters. The invention makes it possible to increase the reliability of the shift register, implemented on the basis of one-bit memory modules 1 and counter 2 with a conversion factor n, by checking the correctness of its operation (n is the capacity of the one-bit memory module; m n is the device delay for shifting ticks). The control is performed by comparing the output information of the device, delayed by one clock by the output D-flip-flop 6, with information arriving at the input of the device and delayed by m p - (1 clock-stroke by the input D-flip-flop 5 and divider 4. The comparison is made by modulo 9 The time required to monitor the health of all the memory modules is (m n + 1) n cycles. 1 or. (L I Sd SAE SP

Description

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The invention relates to computing and can be used, for example, in building lines, delays for digital filters.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a functional diagram of the device.

The device for shifting with self-control contains ha of single-bit memory modules 1, counter 2 with a recalculation coefficient n (n is the capacity of a single-bit memory module, m n is the delay of the shift register in cycles), 1H + 1 buffer triggers (BT) 3, divider 4 with the division factor m p + input 5 and output 6 D-flip-flops, the element NOT 7, the element And 8 and the adder 9 modulo two. The drawing also shows information inputs 10 and output 11, the first 12 and second 13 clock inputs, the control output 14 of the device, the 15 potential potential bus 15 Clock pulses at inputs 12 and 13 have a period T, a duration T / 2, and TI2 pulses (input 13 ) are ahead of TI1 impulses (input 12) by T / 4 "

The shifter operates as follows.

Suppose that in the first cycle of operation of the device, the address inputs of the memory modules 1 from the outputs of counter 2 receive a code corresponding to the choice of the cells with the O number, i.e. counter 2 is in the zero state. Close

Moreover, suppose that in this device operation cycle at the first output of divider 4 there is a first negative pulse, the duration and position coinciding with the positive signal half-period at input 13. We take the bit of information received at input 10 of the device in the first cycle. This bit. The positive edge of the TI1 clock pulse at input 13 is recorded in BT 3, the positive (back) front of the pulse from the first output of the divider 4 and the same information bit is written to the input D-flip-flop 5, where it is stored until the positive edge of the second Impulum from the first output arrives divider 4 (this pulse is generated in the (mn + 1) th cycle). Then, when TI1 1, the first bit is written into the cell number O of memory module 1,. In the second cycle, the cells with the number 1 of memory modules 1, etc. were selected. B (n + 1) th

The counter 2 returns to the zero state, the device enters the (n + 1) -th bit of information and the cell number 0 is selected again. The first bit of information at TI1O is read from memory module 1, and the positive edge of the clock pulse TI2 is recorded in WT 3, from the output of which at TI1 1 is rewritten into the cell with the number O of the memory module 1. In the (2n + 1) -th cycle, the first bit from the output of BT 3, with the TI1 1 is copied into the cell with the number O of the memory module ti 1 and so on In the nth bar

5, the first bit at TI1 0 is read out from memory module 1, a positive edge of the TI2 clock pulse is rewritten into WT 5 rt and is output to the device. The second bit of information in the second cycle is recorded in the cell with number 1 of memory module 1, in (n + 2) -th cycle - in BT 3 and from its output into cell with number 1 of memory module 1, j, etc. . and in (Fri + 1) th cycle

5 enters the output of the device; The nth bit of information in the above order sequentially passes the cells with the n-1 number of the memory module 1 and, in the (f + n-1) -th cycle, arrives at the output of the device. Then the specified process of promoting information on

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memory module repeats.

Thus, the output implements the function of a sequential n-bit shift register, the signal at the output of the BT 3, (where, t) is delayed with respect to the signal at the output of the BT 3, i i also so that This device as a delay line with taps for a digital filter.

The first bit of information in the PCG-m5 from the output of the device by the positive edge of the clock pulse TI1, inverted by the NOT 7 element, is written to the output D-flip-flop 6 ,. where it is kept until the end of (pga + 1) th tak0 ta. The output signals of the input 5 and output 6 D-flip-flops arrive at the inputs of the adder 9 modulo two, which, if they do not match, produce a signal 1. If the cell with

5 number About any of the memory modules 1 is faulty, then in (pga + 1) -th cycle at the inputs of the input element And 8 simultaneously there is a signal 1 from the output of the adder 9 modulo two and put

The main pulse from the second output of divider 4, as a result of which at the output of element 8, which is the control output of the device, produces an error signal in the form of a positive pulse coinciding in position and duration with the pulse at the first output of divider 4. In the same (Fri + The 0th pulse of the positive edge of the second pulse from the first output of the divider 4 in the input D-flip-flop 5 is recorded (Fri + 1) -th bit of information which in the above order passes sequentially the cells with the number 1 of memory modules 1 and by analogy with the described you e serviceability controlled cell number 1. Further, this process is repeated for cells with other numbers, resulting in a time (m + 1) cycles controlled claim serviceability of all the cells of all models from memory.

Formula 1 goat

A device for shifting with self-control, containing m single-bit memory modules, t + 1 buffer triggers and a counter with a conversion factor n (n is the capacity of the single-bit memory module, nm is the delay of the device for shifting in cycles), and the sampling resolution inputs one-bit memory modules are connected to the device potential zero bus, and the recording resolution inputs and the counter input are the first clock input device Compiler A. Deryugin Editor M. Andrushenko Tehred I. Popovich Corrector M. Sharoshi

5570/51

Circulation 588 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

ten

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the counter outputs are connected to the address inputs of single-bit memory modules, the information input and output of the i-ro single-bit memory module (, ha) are connected respectively to the output of the i-ro and to the D input (i + 1) -ro of the buffer the trigger, the D input of the first and the output of the last buffer triggers are, respectively, the information input and output of the device, the C inputs of the buffer triggers are the second clock input of the device, characterized in that, in order to increase the reliability of operation of the device, a divider with a factor business and TP + 1, input and output D-flip-flops, modulo two adder, the element is NOT and the element is AND, the divider input is connected to the C-input of the buffer trigger, and the first output - to the C-input of the D-flip-flop, D-input which is connected to the D input of the first

25 buffer trigger, and the output - with the first input of the modulo two adder, the second input of which is connected to the output of the output D-flip-flop, the D-input of which is connected to the output of the last buffer trigger, and the C-input - to the output of the HE element, whose input connected to the write enable input of the first one-bit memory module; the output of the modulo-two adder is connected to the first input of the AND element, the second input of which is connected to the second output of the divider, and the output is the control output of the device.

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Claims (1)

Formula zobre.teniya A self-checking shift device containing w one-bit memory modules, w + 1 buffer triggers and a counter with a conversion factor η (η is the capacity of a one-bit memory module, fr is the delay of the shift device in clock cycles), moreover, the sampling resolution inputs of one-bit memory modules are connected with the bus of the zero potential of the device, and the recording permission inputs and the counter input are the first clock input of the device, the counter outputs are connected to the address inputs of single-bit memory modules, the information input and output i-ro are single memory module (i = 1, w) are connected respectively to the i-ro output and to the D-input (i + 1) -ro of the buffer trigger, the D-input of the first and the output of the last buffer triggers are respectively the information input and output of the device, C -Log buffer triggers are the second clock input apparatus ₁₅ characterized in that, in order to increase the reliability of the device, it introduced divider with dividing factor wn + 1, the input and output Dtriggery adder modulo two, 2Q element and an aND NOT wherein the input of the divider is connected to the C-input m of the buffer trigger, and the first output is with the C-input of the input D-trigger, the D-input of which is connected to the D-input of the first 25 buffer trigger, and the output is with the first input of the adder modulo two, the second input of which is connected to the output of output D -trigger, the D-input of which is connected to the output of the last buffer buffer trigger, and the C-input is the output of the element NOT, the input of which is connected to the write enable input of the first one-bit memory module, the adder output modulo is two connected to it with the first input of the AND element, the second input of which is connected to the second output m divider, and the output is the control output of the device.