SU1322269A1 - Device for extracting root of sum of squares of three numbers - Google Patents

Abstract

The invention relates to computing and can be used in digital computers for hardware calculating the function D + Y +. The purpose of the invention — device simplification — is achieved by introducing into a device containing five registers, four groups of elements AND 4-8, 9- 12 and three adders 13-15, trigger 17, the element NOT AND the corresponding connection of the circuit elements. 2 Il. (L

Description

The invention relates to computing and can be used in digital computers for hardware calculation of the function D + Y +.

The purpose of the invention is to simplify the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - diagram of the connection of the elements of the group and the register.

The device contains inputs 1-3, respectively, of the first, second and third arguments of the device, registers 4-8, groups 9-12 of elements AND, adders 13-15, element NOT 16, trigger 17, start input 18, input 19 logical zero, input 20 device synchronization, outputs 21 and 22 of the result of the device, And 23 elements (in groups 9-11), outputs of 24 elements And groups.

Registers 4-6 are the usual n-bit shift registers, register 7 is the shift register containing the (p-1) bits. All registers are controlled by input 18 of the device. Trigger 17 is a normal D trigger. On input S, it is controlled from inputs 18, the sync input C is connected to input 20 of the device.

The device works as follows.

Before starting work with input 1-3 in registers 4-6 c) yd ts variable X, Y, Z, respectively. Reg Ist 8 reset D. zero. The calculation of the function D requires the execution of (n + 2) th cycles. Since all cycles are the same, we limit our consideration to i-ro unK.ria.

The cycle starts with a signal C at the input 18 of the device. On this signal, the contents of registers 4-7 are shifted one bit to the left. Zeros are written to the 4–6 bits of the registers. The lower bit of register 7 is written to the bit of function D formed in the previous cycle in trigger 17. At the same time, trigger I7 goes to the single state. Register 8 will record the amount formed in adders 14 and 15 in the previous cycle.

Upon completion of the shift and writing to

The outputs of groups of elements And 9-1 form partial squares X.,

Y., Zr, which are summed up in adders 13 and 14. Simultaneously, the outputs of the trigger 1 7 and the hologts of the elements And 12 form a partial square D; on the assumption that the i-th bit of DD. equal to i with a minus sign.

The sum 15 is generated in the adder 15.

 X Y Y. ± Z

-.r: J fr: 1 M J

 “R

j

Upon the decay of the transients, a signal C is fed to the input 20. If S 5 O, the trigger 17 remains in one state (D 1). If, in the trigger 17, the inversion of the sign of the sum S is written, i.e. it will go to the zero state (D 0). Upon the decay of transients caused by signal C, the cycle ends. At input 18, the next signal C is supplied, and the next cycle is performed. After the (n + 2) -th cycle is executed, the low-order bit of function D will be recorded in trigger 17, and the remaining bits will be recorded in register 7.

five

0

five

0

five

0

Claims (1)

Invention Formula A device for extracting the root from the sum of squares of three numbers, containing five registers, three adders, four groups of elements AND, and the information on the inputs of the first, second and third registers are respectively the inputs of the first, second and third arguments of the device; Moreover, for the sake of simplicity, it contains a trigger and an NOT element, with the first inputs of the AND elements of the first, second and third groups being connected to the direct outputs of the high-order bits, respectively, of the first, second and third registers, second entrances ne of the first and second elements of the first, second and third groups are connected respectively to the direct and inverse outputs of the second discharge of the respective registers, the direct outputs of the bits from the third to the nth, where n is the width of the first, second, third and fourth registers are connected to the second inputs of the corresponding elements AND of the first, second and third groups, the outputs of elements AND of the first and second groups are connected respectively to the first and second groups of inputs of the first adder, the outputs of which are connected to the first e-VOY group of inputs torogo adder, whose second group of inputs connected to the outputs of AND gates of the third group, the control inputs of all registers vi S-trigger input connected to the the trigger input of the device, the trigger trigger input is connected to the device synchronization input, the outputs of two lower bits of the second adder are connected to the inputs of two lower bits of the fifth register, n-1 higher bits of the second adder are connected to the inputs of the lower bits of the third adder, input The () -th bit of which is connected to the input of the logical zero of the device, the inputs of the first (n + 1) -th and () -th bits of the third adder, the first inputs of the elements of the fourth group and the information input of the fourth register are connected to the direct output trigger inverse w.yho The bits of the fourth register are connected to the inputs of elements AND of the fourth group, the outputs of which are connected to the first inputs from the second to the fifth bits of the third adder, the outputs of the fifth register are connected to the second inputs of the third adder, the outputs of which bits the register is shifted by two bits in the direction of the higher bits, the output of the higher bit of the third adder is NOT connected to the D input of the trigger through the terminal, the direct outputs of the fourth register and the trigger are output devices of the device.