SU1322262A1 - Device for summing n numbers arriving in sequential order - Google Patents

Abstract

The invention relates to computing and can be used in devices for statistical processing of information. The purpose of the invention is to increase speed. A device for summing m successively incoming numbers contains first and second registers 1 and 2, counter 3, random access memory 4, subtractor 5, accumulating adder 6, Pulse generator 7, information inputs 8, clock input 9, reset input 10, result outputs 11 . 2 Il. with f f // J oo 1C ko and a tsD I j u. one

Description

The invention relates to a computing technique and can be used in devices for statistical processing of information.

The purpose of the invention is to increase the speed.

Fig. 1 is a functional diagram of the device for summing m sequential incoming numbers; FIG. 2 shows timelines of the operation of the device.

The device for summing m successively incoming numbers contains the first 1 and second 2 registers, counter 3, random access memory A, calculator 5, accumulating adder 6, pulse shaper 7, device information inputs 8, device clock input 9, device reset input 10, output 11 results of the device, the subtractor contains the n-bit adder I2 (where n is the operand size) and n elements NOT 13, the accumulating adder contains N-bit 14 and the register: 15 (where K p + log.m), the pulse shaper contains odd th number of elements is not 15, and elements 17, an odd number of elements is not 18

Registers 1 and 2 are dynamically configured with input C, and information is recorded in them. front edge of the strobe signal. Counter 3 is triggered on the falling edge of the counting iiMnyjTbca and the mocket is to be executed on a K155 IE7 chip. Random access memory 4 has n bits and r address inputs. With a zero signal V, information is recorded, with a single signal, counting.

The shaper 7 is designed to generate an inverse pulse signal delayed relative to the leading edge of the clock signal. When the input signal of the shaper is changed from zero by one, the NOT 16 elements at the inputs of the H 1 7 element are set to single signals. A single pulse signal from the output of the element And 17 is delayed and inverted by the elements NOT 18. When the shaper 7 is executed on the mixture, elements F1E of the type K155. PI and element And type LN1, the duration of the output pulse of the driver is 45-75 not, and the delay from

about the leading edge of the clock signal 60-100 not,

The device inputs 8 are supplied with parallel p-bit binary codes of summable numbers with a frequency equal to the frequency of the clock signal supplied to input 9. For the device to work properly, it is necessary that at the time the clock signal changes from zero to one the information on the inputs 8 is reliable. Negative numbers are fed to inputs 8 in the additional code, while the highest nth bit is significant. A single signal is applied to input 10, which sets the device to its initial state.

A specific variant of the device according to FIG. 1 is complete, N 16, g 8, m 256,

The device works as follows.

After power is turned on, input 10 is given a signal that holds the register I and accumulates the adder 6 in the zero state, Count: IR 3 continuously counts the clock pulses, while at its output codes are generated that enumerate the addresses of the random access memory 4, and the pulse ones the signals from the output of the imager 7 is written in the cell with these addresses zero codes,

In order to ensure the storage of the memory cells 4, the duration of the reset signal must be more than T T. At the end of the process of zeroing, zero codes are set at the outputs of the register 2 and the subtractor 5. At the end of the reset signal. the leading edge of the clock signal in register 1 is written the first number C, which enters through subtractor 5 into accumulating adder 6 and is written into the RAM cell with address A, the Start Address Ad is determined by the state of counter 3 at the moment of the end of the reset signal and is a random number ,

During the first m cycles, the first m numbers are written into the RAM, and zero codes are read, since reading the code from the random access memory at address A; and writing it to register 2 is done by writing code at this address.

su. Code B, in the accumulating adder during the first m cycles, is formed according to the expression Bj B +

+ C. at 1 1, t, where C is the code in register 1 in the i-th cycle, and B. In the ,, -g code in the accumulating adder 6, respectively, in the i + 1 and i-oM ticks.

The (t + 1) -th cycle of operation in register 2 records the code C ,, recorded m cycles back into the cell A of the operational memory fO, and at the output of the subtractor 5 a code C is formed equal to C - C. In the i-M cycle with i 7 m at the output of the subtractor 5 will be a code C, equal to C, - C ,. ff

Consequently, code B., is changed by law.

B, + C j with i i t; B + C. + C. at i m

t 1 1-gt1

and is equal to the last m numbers that arrive in series at the inputs 8 of the device,

The number m is determined by the conversion factor of counter 3 and can be arbitrary. If m 2, n the most significant bits of the output code paBni.i is the arithmetic mean of m consecutively received numbers.

The operation of the device during one cycle can be traced along the time diagrams (Fig. 2). The diagrams are presented for a specific device, 35 implemented on K155 series chips at a clock frequency of 2 MHD and a duration of 300 ns (Figure 1). The state of counter 3 varies along the trailing edge of the clock signal 40 (diagram 2), the time T is equal to the duration of the transient process in counter 3. Diagram 3 shows the state of the output signal at the output of the operational storage device 4 45.

During the time T, and t in the random access memory 4, there is a transition process associated with the change of address, and during time 4 a transition process associated with the recording of new information. Information can be copied from the RAM during TI or Tj, while at time 1, the previously recorded information at this address is read, and at the time of the newly recorded information.

50

g

O ff

0

five

0

: b24

The output signal (10mirovator 7 has a duration f and a delay 1 with respect to the leading edge of the clock signal. Diagram 5 shows the output state of the registers 1, 2 and 14, which varies on the leading edge of the clock signal with a delay T due to the switching time It should be noted that the writing into the register 2 of the code from the random access memory 4 takes place during T, so that in the register 2 the code written into the random access memory is remembered. ago.

It can be seen from diagram 6 that the transition process in adder 13 starts after updating the information in registers 1, 2 and 14 and ends after time Td. The transient must end earlier than the front of the clock signal, and the code from the output of the adder 13, which must be stable over time, is rewritten into register 14,

From diagrams 1-6, it follows that transients in adders have the longest duration, and the duration of the summation cycle is equal to

+ g

5 And determined mainly

time t, The period T of the clock signal must be greater than

The duration T, is determined by G (N + 1) 1, where T is the response time of one bit of the combinational adder.

Claims (1)

Invention Formula A device for summing m consecutively incoming numbers containing a accumulating adder, first and second registers, the outputs of the accumulating adder being connected to the outputs of the device result, characterized in that, in order to increase speed, a counter, a random access memory, a pulse driver, a subtractor are entered into it containing an n-bit dr1 adder (where n is the operand width) and n elements of NOT, the accumulating adder contains an N-bit adder and register (where N l +), and information inputs of the first register are connected to the corresponding bits of the device operands, the device input clock is connected to the synchronization inputs of the first and second register and accumulator accumulator register, the trigger input of the trigger and the pulse driver input, the output of which is connected to the write and read control input memory devices whose address inputs are connected respectively to the output of the counter, the outputs of the first register are connected respectively to the information and the inputs of the random access memory and are connected respectively to the information inputs of the first group of p-bit adders, the inputs of the second group of which are connected respectively to the outputs of the elements of the NOT subtractor, the inputs of which are connected respectively to the outputs of the second Compiled by M. Yesenin Editor P. Gereish Tehred D. Kravchuk Proofreader S. Shekmar 2864/44 Circulation 672 Subscription VNINGP1 USSR State Committee for inventions and discoveries 13035, Moscow, Zh-35, Raushsk nab. A / 5 Production and Printing Enterprise, Uzhgorod, st. Project, 4 222626 the register, informational inputs of which are connected respectively to the outputs of the random access memory, the transfer input of the n-bit d-5 adder is connected to the input of the logical unit of the device, the outputs of the n-bit adder are connected respectively to the inputs from the first to the nth first group N- discharge sum- mat, the inputs of the first group with (n + 1) - th to N-th of which are connected to the output of the n-th discharge of the n-bit adder, the inputs of the second group of N-bit adder are connected respectively with register accumulation su mmator and connected respectively to the outputs of the accumulating adder, the device reset input is connected to the installation inputs of the first 0 register and accumulating adder register, the information inputs of which are connected respectively to the outputs of the N-bit adder.