SU1675849A1 - Digital linear interpolator - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in output graphic devices with linear and matrix registration bodies, in computer-controlled machine tools that use linear and matrix executive bodies. The purpose of the invention is to reduce the error of approximation of the interpolator. The digital linear interpolator ensures finding the multi-bit increments with which a given segment of the straight line is approximated in one interpolation cycle, and then passing the generated multi-bit increments through the alignment unit, as a result of which the uneven distribution of the single impulses decreases in the indicated groups. Due to this, the approximation error is halved. The value N of the lower bits of the M-bit coordinate increments is stored in registers 2 and 3. MN of the higher bits of the coordinate increments are fed to the address inputs of the permanent memory unit 4, from the outputs of which 2 N-1 bits of the increments are written to registers 9 and 10. The least significant bit of 2m m-bit increments is formed by N-bit binary multipliers 5 and 6, in sl

Description

QS

ate

00

N o

the informational inputs of which, from the outputs of registers 2 and 3, receive the values N of the lower bits of the coordinate increments X and Y, respectively. The information inputs of the leveling blocks 20 and 21 receive the values of the generated 2M N-Pasc increments, and from their outputs,

corresponding to the leading and driven coordinates, these values are read by an external device. The interpolation of a given straight line segment takes place in 2N + 1 interpolation cycles. The control unit 1 synchronizes the operation of the interpolator. 2 hp f-ly, 4 ill. 1 tab.

The invention relates to automation and computing technology and can be used in output graphic devices with linear and matrix registration bodies, in computer-controlled machine tools that use linear and matrix executive bodies.

The purpose of the invention is to reduce the error of the approximation of the interpolator.

FIG. 1 shows a block diagram of a digital linear interpolator; in fig. 2 - functional diagram of the implementation of the control unit; Fig. 3 is a functional diagram of the alignment unit implementation; in fig. 4 shows an example of approximation of a given straight segment, respectively, for a known and a given interpolator.

The digital linear interpolator contains control block 1, the first 2 and second 3 registers of coordinate increments, block 4 of the fixed increment memory, the first 5 and second 6 binary multipliers, the first 7 and second 8 triggers, the first 9 and second 10 registers, input 11 start, write input 12 on the master coordinate, information input 13, input on the slave coordinate input 14, gate output 15, interpolation end output 16, set 17 and signal 18 outputs of the control unit, input 19 of the initial interpolator setting, first 20 and second 21 alignment units formation outputs on the leading 22 and on the slave 23 coordinates. The control unit 1 contains a pulse generator 24, the first 25, the second 26, and the third 27 And elements, the first 28 and the second 29 D triggers, and the counter 30.

Each alignment block 20 and 21 contains EXCLUSIVE OR elements 31i, 312, ... 312H-1312M N, elements AND 32i, 322, ... 322H-i,, D-flip-flop 33.

The control unit 1 is designed to synchronize the operation of the interpolator.

The first 2 and second 3 coordinate increment registers are used to receive and store the N lower bits of the M-bit coordinate increments X and Y, defining

specified segment pr my. The increments X and Y are received at the input 13 of the interpolator to successively in time. The entry of the N least significant bits of the coordinate increment into the first register 2 of the coordinate increment is performed by a single level at the input 12 of the interpolator. Writing N low bits in the second register

The 3 coordinate increment is produced by a single level at the input 14 of the interpolator. The outputs of the first register 2 coordinate increments are connected to the information inputs of the first binary multiplier 5, the outputs of the second register 3 coordinate increments - to

information inputs of the second binary multiplier 6.

The principle of operation of the binary multiplier 5 and 6 of this interpolator is similar to the principle of operation of the binary multiplier 5

and 6 — a sequence of pulses is formed, proportional to the weights of the control code at its information input.

The organization of the block 4 of the permanent memory of increments is the same as in the known interpolator. Block information capacity

4 incremental incremental memory is calculated by the formula

E - (-1)

when organizing x 2m m-1-bit words.

Block 4 of the constant increment memory serves to store bits

2 m-bit increments generated per interpolation beat. The incremental memory block 4 is connected by address inputs to the higher-order M-N bits of the interpolator information input 13, through which the values of the coordinate increments D x and L y are received successively in time. The first 5 and second 6 binary multipliers serve

forming the value of the lower bit of 2 m-bit increment, formed in one interpolation cycle. The output of the first binary multiplier 5 is connected to the information input of the first trigger 7, which serves to fix

l M-HF

the low-order bit is a 2-bit increment generated by one interpolation cycle along the X coordinate. The output of the second multiplier b is connected to the information input of the second trigger 8, which serves to fix the low-order bit 2-bit increment generated by one interpol time tick on Y coordinate.

The first 9 and second 10 registers are used to store 2m -1 bits of 2-bit increments along the X m Y coordinate, respectively. Their values remain unchanged until the arrival of new source data.

Writing the value of 2m m-1 bits of 2 m m-bit increments generated during one interpolation cycle to register 9 is performed from the outputs of block 4 of the fixed memory increments when there are higher-order bits of the coordinate increment X and when a signal of a logical unit arrives at the input 12 of the interpolator. The values of 2m – 1 bits of 2 m m-bits increments generated during one interpolation beat in the second register 10 are made from the outputs of block 4 of constant memory, if there are higher-order bits of the coordinate increment Y at its address inputs MN and on arrival signal of the logical unit to the input 14 of the interpolator.

Alignment blocks 20 and 21 are identical throughout the structure and serve to equalize the uneven distribution of single pulses in groups of elementary increments along the driving and driven coordinates, generated respectively at the information outputs along the driving and driven coordinates, as a result of which the approximation error is halved. The information input of the higher bits of the information word of block 2 alignment receives the values of the higher bits of the 2nd m-bit information word, and the information input of the lower bits of the information word is the value of the younger bit. The gating input of the alignment units 20 and 21 is connected to the gating output 15 of the interpolator. The setup input of the alignment units is connected to the input 19 of the initial

installation interpolator The information output 22 of block 20 corresponds to the leading coordinate, and the information output 23 of block 21 to the slave coordinate.

The pulse generator 24 in the control unit 1 serves to generate a pulse sequence that clocks the operation of the control unit 1. The logical zero signal at the output 16 of the interpolator signals the end of the interpolation of a given straight line segment and the readiness of the interpolator to accept the coordinate increment values of the new straight line segment.

The output of the second element AND 26 is the gate output 15 of the interpolator. The value of the logical unit at the specified output signals the reliability of the output data at the information inputs 22 and 23 of the interpolator. The output of the first element AND 25 is connected to the read input of the first 5 and second 6 binary multipliers and the recording input of the first 7 and second 8 flip-flops, and is also connected to the subtractive input of counter 30. Counter 30 serves to generate a negative polarity pulse at the end of the reproduction of a given segment of pr my after the device has been working 2 interpolation cycles. Before the start signal arrives, the counter 30 is in the mode of recording the contents of the information bits in the counter, since from the direct output of the D-flip-flop 20 a logical zero signal is received, which is active relative to the write signal to the counter 30. The information input of the counter 30 the installation method enters the value of 2m + 1.

The first input of the third element 27 And is connected to the input 19 of the initial installation of the interpolator. The negative signal at the specified input is the first 28 and second 29 D-flip-flops, the first 5 and second 6 binary multipliers are set to the zero state, since the output of the third element And 27 is connected to the R-input of the first 28 and second 29 D-flip-flops and the setup input of the first 5 and second 6 binary multipliers. The second input of the third element AND 27 is connected to the transfer output of the counter 30. The control input of the D-flip-flop 29 is connected to the input 11 of the start of the interpolator, and the information D-input 29 of the D-flip-flop 29 is connected to the input of the logical unit.

The interpolator works as follows.

The basis of the invention lies in the possibility of unambiguously forming a group

from 2m N of elementary increments along the leading and driven coordinates by the algorithm, and then leveling the uneven distribution of single pulses in the specified groups using alignment blocks 20 and 21. As in the known device, in this linear interpolator, the value of N lower bits of M-bit coordinate increments is stored in registers 2 and 3. M-N higher bits of coordinate increments are sent to the address inputs of the 4 fixed memory block, from the outputs

  .

which 2 -1 -shapes of increments are recorded in registers 9 and 10. The low bit of 2m m-bit increments is formed by an N-bit binary multiplier 5 and b, the information inputs from which are output from registers 2 and 3 are N- the lower bits of the coordinate increments X and Y, respectively. Thus, the procedure for forming 2 m-bit groups of elementary increments at the outputs of registers 9, 10 and triggers 7, 8 is carried out in the same way as in the known interpolator. Then, these groups arrive at the information inputs of the alignment units 20 and 21 and undergo the alignment procedure, i.e. non-uniformity of single pulses in groups of multi-bit increments decreases. After that, the multi-bit increments are read to the external device.

Consider the alignment procedure using blocks of 20 liters 21. Since these blocks are identical, consider the principle of operation of block 20, which corresponds to the leading coordinate. The alignment procedure consists in unambiguously obtaining a 2m-bit group of elementary increments, in which the distribution of single pulses is the same as if one passes two elementary increments through the sequential-step-by-step method through a counting trigger. For example, let the code 10100101 be sent to the information inputs of the alignment unit 20. If such a code combination is passed through a counting trigger, we get 10000100. Therefore, the output of the alignment block in each interpolation cycle should be uniquely obtained with the code 10000100. In addition, the value of the last (lower ) the bit of each group being formed and the value of the first (senior) bit of each subsequent group should follow the rule according to the alignment procedure. For example, let the informational inputs of the block

20 alignment in two interpolation cycles, code 10100101/10100100 is received. Then, at the output of the alignment block, after two interpolation bars, we get the code

10000100/10000100.

It should be noted that the interpolation of a given segment of a straight line in a given interpolator is carried out in 2N + 1 interpolation cycles, and in the known

0 interpolator for 2 interpolation cycles. A twofold increase in the number of interpolation cycles is due to the fact that the number of unit steps in multi-bit groups after the equalization procedure is reduced by a factor of two.

The control unit 1 operates as follows. The negative polarity signal at the input 19 of the initial installation of the second

29 and the first 28 D-flip-flops are set to the zero state. Consequently, at the outputs 15-18, the values of a logical zero are set. Since at the direct output of D-flip-flop 29 a logical zero value is generated, then in the counter

5 30, a value of 2 is recorded, formed by the assembly at its information input.

When a signal of a logical unit arrives at the input 11, the interpolator starts

0 A D-flip-flop 29 is set to the state of a logical unit, thereby enabling counter 30 to operate in a counting mode. In addition, this signal enters the output 17 of the control unit 1 and enables

5 operation of the first 5 and second b binary multipliers. The leading edge of the pulse arriving from the direct output of the generator of 24 pulses, the first D-flip-flop 28 is set to the logical state

0 units, because its information input receives a logical unit signal from the output of the second D-flip-flop 29. The described actions ensure strict synchronization of the interpol 5 cycle to the leading edge of the pulse generated by the pulse generator 24 after the signal of the logical unit arrives at the 11 input of the interpolator . With each pulse from the generator output

0 24 pulses with a single value of the first D-trigger 28 counter value

30 is reduced by one. When the transition of the counter 30 from the zero state to 2, where N + 1 is the size of the counter, on its

5, the transfer output P is formed by a negative polarity pulse, which sets the second D-flip-flop 29 to the logical zero state. With the appearance of the leading edge of the pulse from the 24-pulse generator, the first D-flip-flop 28 also

is set to the state of logical zero, prohibiting the passage of pulses to the output of the first 25 and second 26 elements I. In addition, the logical zero signal from the output of the first D-flip-flop 28 is output to the output 16 of the interpolation end, signaling the end of the interpolation of the segment. The number of pulses generated from the outputs of the first 25 and second 26 elements And for the interpolation cycle is 2N + 1.

Consider the direct interpolation of a segment in a numerical example: let,,,. The number of interpolation ticks is 2–8. In each interpolation tick, 4-bit increment groups are formed along the leading and driven coordinates. Consider the alignment procedure for driving and driving coordinates. The data is summarized in the table. Obviously, the procedure for forming multi-bit increments arriving at the information inputs of blocks 20 and 21 is the same as in the known interpolator.

The marked value in the lower order is generated by the first 7 or second 8 trigger.

The values of multi-digit groups for the known interpolator in the table are in the rows of Information. input block 20 and info. the input of block 21 for four informational cycles, since the interpolation cycle in the known interpolator constitutes the interpolation cycle. For clarity, FIG. Figure 4 shows a graphical example of the approximation of the considered given straight segment, respectively, for the known and given interpolators.

As the element base of the interpolator, commercially available microcircuits of the series 155.555.531.589.176 are used.

The alignment unit 20 and 21 can be implemented in various ways, FIG. 3 presents one of the options for implementing the specified block. The specified block generally consists of 2L EXCLUSIVE OR 31 and 2 AND elements, which serve to separate the bits of the multi-bit increment, taking into account the alignment procedure. D-flip-flop 33, which is part of block 20 and 21, is used to fix the value of the lower 2 N-ro bit of the output multi-bit increment, since the value of the high bit of each generated multi-bit increment and the value of the first bit of each subsequent multi-bit

Ele, MN

tact increments are subject to the alignment procedure.

The control unit 1 is implemented on the elements K155 TM2, K155 LI1, K155 IE7; ; - “registers 2,3,8,10 triggers 7,8-on K155TM7 elements, block 4 of the incremental constant memory - on K155 REZ elements, binary multipliers 5, 6 - on K155 IE8 elements, alignment blocks 20, 21 on elements

K155LP5, K155LI.

The introduction to the interpolator of blocks 20, 21 of alignment along the leading and the driven coordinates ensures the alignment of the distribution of unit values in 2M-Nd of step increments by averaging the unit values in each such group.

In this interpolator, by introducing alignment blocks 20, 21, the nonuniformity of stepping increments is reduced in parallel in the whole group of bits, i.e. the role of the alignment unit for a group of multi-bit increments is similar to a counting trigger for

sequences of elementary increments. Consequently, it can be concluded that the approximation error in the groups of bits of the multidigit interpolator increments decreases.

2 times.

In the famous interpol torus, the maximum error

(Zoo + 7 + OU-2 J + t)

18

where u is the resolution of the initial increments.

This technical solution reduces the approximation error by half. Thus, the maximum error

 Max

Omaks -

(3y + l + (- rf + 1) 36

45

Claims (3)

Claim 1. Digital linear interpolator containing control unit, first and second registers of coordinate increments, block of constant memory increments, first and second binary multipliers, first and second triggers, first and second registers, input of the second register entry connected to the input of the record of the second registrar 55 pa coordinate increments and with the input of the record on the slave coordinate of the interpolator, the record input on the leading coordinate of which is connected to the record input of the first register of coordinate increments and to the record input register, whose information input is connected to the information input of the second register and with the output of the incremental memory block, whose address inputs are connected to the MN senior bits of the information input of the device, N the lower bits of the information input of the device are connected to the information inputs of the first and second registers coordinate increments, the information output of the second register of coordinate increments is connected to the information input of the second binary multiplier, whose information output is the same information input of the second trigger, the recording input of which is connected to the recording input of the first trigger, the signal output of the control unit and the read input of the first and second binary multipliers; the input input of the second binary multiplier is connected to the installation output of the control unit and the installation input of the first binary multiplier; information input which is connected to the information output of the first register of the coordinate increment, and the information output of the first binary multiplier is connected to the information The first trigger input, which builds the output of the control unit, is the gating output of the interpolator, the output of the interpolation end of the control unit is the output of the interpolation end of the interpolator, and the start input of the control unit is the start input of the interpolator, characterized in that in order to reduce the approximation error of the interpolator, the first and second alignment blocks are entered into it, the information inputs of the higher bits of the information word are connected to the information outputs of the first and second On the registers, respectively, the information inputs of the lower bits of the information word of the first and second alignment units are connected to the outputs of the first and second triggers, respectively, the input of the initial installation of the interpolator is connected to the input of the initial installation of the control unit and the installation inputs of the first and second alignment blocks, the gates of which are connected with the gate output of the control unit, and the information outputs of the first and second alignment units are the information output of the interpo trator on the leading coordinate and information output of the interpolator on the driven coordinate, respectively. 2. Interpolator according to claim 1, characterized in that the control unit comprises a pulse generator, first, second and third elements AND, first and second Dtriggers, a counter containing information inputs for 2N + 1 bits, with the start input of the block and the input of the initial installation of the block is connected to the control C-input of the second D-flip-flop and to the first the input of the third element And, respectively, the installation R-input of the second D-flip-flop is connected to the output of the third element And and the installation R-input of the first D-flip-flop, the information D-input of which is connected to the output of the second D-flip-flop, the installation output of the control unit and the installation input counter, the subtracting input of which is connected to the signal output of the control unit and the output of the first element And, the first input of which is connected to the direct output of the pulse generator and the control C-input of the first D-flip-flop, the first input of the second element And is connected to the inverse output of the pulse generator, the output of the first D-flip-flop is connected to the second inputs of the first and second And elements and with the output of the interpolation end of the control unit, the gate of which is connected to the output of the second element AND, the information D input of the second D-flip-flop is connected to the bus of the logical unit, the transfer output of the counter is connected to the second input of the third element I. 3. Interpolator pop, characterized in that each alignment block contains 2M N elements EXCLUSIVE OR, AND elements (where M is the maximum coordinate size increments, N is the number of lower-order bits of the coordinate increments A X and A Y), D-flip-flop, the control C-input and the set-up R-input of which are the control and the set inputs block, respectively, the output of the D-flip-flop is connected to the first input of the first element EXCLUSIVE OR, the output of which is connected to the first input of the second element EXCLUSIVE OR, the output of which is connected to the first input of the second element AND and to the first input (2N-1) of the element EXCLUSIVE OR, the output of which is connected to the first input (2JH-1) -ro of the AND element (where , ..., M, N) and to the first entrance The 2nd m of the EXCLUSIVE OR element, the output of which is connected to the first input of the 2nd m element AND and to the information D input of the D flip-flop, the second the input of the first element EXCLUSIVE OR is connected to the second input of the first element AND, the second input of the () element EXCLUSIVE OR is connected to the second input (2 | -1} -th element AND, the second input of the 2nd element of the EXCLUSIVE OR connected to the second input 2 N-ro element And, the second inputs from the first to (2n-1) -th elements EXCLUDE five with Log 29 g Fig 2 ALSOR OR is connected to the information input of the higher bits of the information word of the block, the information input of the lower bits of the information word of which is connected to the second input of the EXCLUSIVE OR element, the output of AND elements are connected to the information output of the block. Ј77 s; Jhu1 / -i -P-i 3-0 4-i / 5th 6th 7th about g g j 4 s b 7 8 9 w ft gn 6 Fig.4 45 33