SU1244786A1 - Digital filter - Google Patents

Abstract

The invention relates to radio engineering and computing and can be used in digital information processing systems. The quality of the noisy signals filtering. The device performs nonlinear filtering of the input signal according to the Yn – i-i equation. 5) In particular, rank filtering. Binary code The gain PI is written to the memory ratio block 9. n binary codes weight. coefficients e (. (i I, p) are recorded in an n-bit ring shift register (KCP) 5. The content of the 1st bit of the KS 5 is equal to the value (, the m-bit samples of the input signal go to the memory block ( VP) 2. According to the clock pulses of the clock clock 1 pulse generator, the sampling codes of the signal X |., ..., x are in parallel going from the BP 2 to the extremum sequence determination unit 3. In this block, the values of all, r order statistics R ; i) sequence of samples. Sequential statistics are determined by sequential calculation maxima. Element I 4 performs the operation of multiplying the code of the 1st order statistics by weight, 1C (L Figure 1

Description

kozf, (arriving from K (P 5. Signal of g. element I 4 through serial code-to-parallel converter 6) goes to accumulating adder 7. After n cycles, the invention relates to radio engineering and computing and can be used in digital information processing systems .

The purpose of the invention is to ensure the filtration of noisy signals,

Fig. 1 shows the structural electrical circuit of the digital filter in Figs 2 and 3, the structural electrical circuits of the memory unit and the signal extremum sequence determination unit, respectively, included in the digital filter.

The digital filter contains a clock pulse generator 1, a memory block 2, a signal extremum sequence determining unit 3, an AND 4 element, a ring shift register 5, a serial code to parallel converter 6, a accumulator 7, a multiplier 8, a memory block 9 factor, information input 10 digital filter and control input P digital filter.

Memory block 2 contains n registers 12 (where n is the order of the filter), n multiplexers 13, counter 14, information input 15, setup input 16, synchronization input 17, and outputs 18.

The unit 3 for determining the sequence of extremes of the signal contains n elements AND 19, n elements EXCLUSIVE OR 21, n triggers 22 of the first group, n triggers 23 of the second group, selector 24, n information inputs 25, setup input 26 and synchronization input 27.

The digital filter works as follows.

The proposed device generally performs non-linear digital filtering of the input signal according to the following equation:

The digital filter bots binary code from accumulating adder 7 goes to multiplier 8, where multiplication takes place by the coefficient, gain “1 3.p. f-ly, 3 silt,

W.

"L.R

xj,

where Rj (x. „, ..“, x) is the order of the statistics of current samples (samples) of the input signal Y |. - the value of the K-th reference signal at the output of the filter; - a weighting factor having a value of 0 or 1; gain factor. When p 1 and only odd (Y-, then the proposed digital filter performs a rank filtering of the input signal. For example, when j is (n + 1) / 2, where n is odd, the proposed digital filter performs a median filtering signal which is very effective

for smoothing impulse noise. Median 5

With the number (n + 1) / 2 for odd n. If we state that I, in 1 1 J p and p - 1 / n, then we get the usual smoothing filter that implements the sliding averaging using the formula

n b: Before the digital filter starts operating, the binary code of the gain factor p is written into block 9 of the coefficient memory (register), and the n-bit binary code of all the coefficients. i 1 s p is written into; n the bit ring shift register 5, while the content of the i-bit bit of the shift register 5 is equal to the 1st iX, -.

The samples of the input signal, each of which has m bits, sequentially arrive at the information input 1 5 of the memory block 2, simultaneously

The installation input 16 of memory 2 from the control input 11 of the filter receives an impulse to record a new reference and shift the information recorded in n registers 12 of the memory block. In the n go-bit registers 12 time codes of n consecutive samples of the signal x are stored ... x. Block

2 memory also contains n multiplexes 18 and a counter 14 with a conversion factor I equal to m. Using these circuits, sequential bit reading from registers 12 of sample codes x, ..., x is performed, starting from the highest digit. The counting input of counter 14 is connected to a clock output of driver I, which is the output of a clock generator. Thus, with each digital filter cycle of operation, the outputs of memory block 2 in parallel form signals corresponding to the values of a certain bit (using counter 14) of all registers 12.

The sampling codes of the signal xx are parallel in parallel to the corresponding information inputs of block 3. Before the first bits of all n samples are received from memory block 2, all n triggers 23 of the second group are set to one when the pulse is received from control input 11 digital filter. Block 3 sequentially calculates the values of all the order statistics of the sequence of samples stored in block 2 of memory. Sequence statistics are computed by sequentially calculating the maxima of the corresponding sample sequences of the H signal. Using AND 19 EXCLUSIVE OR 21 elements, triggers 22 of the first group, p-input element OR 20, the maximum value of the input code sequence is calculated bit by bit. On the element clause OR 20, the bit t-bit code of the maximum value of the sequence x appears. , ..., x. those. The code of the first order statistics R (x .. 5 fc) S is the result of this, after m cycles of operation of the device, all the triggers 22 of the first group are set to the zero state, except the trigger (s), the number of which corresponds to the maximum count.

five

The selector 24 implements the following function. If the 1st trigger 22 of the first group is in the one state, and all the triggers 22 of the first group with numbers less than i are in the zero state, then on the i-th output of the selector 24 there is a signal 1, and the rest (p-1) outputs of the selector - O. Such a selector

0 can be implemented using n parallel-acting elements And, and K-and element And has (K + 1) inputs. The inputs of the K-th element And are connected respectively with inverse outputs

5 triggers 22 of the first group with numbers lower than K, with direct outputs, K - of the first trigger 22 of the first group and with a clock input of the selector 24,

After calculating all the hectars of maximum bits, the synchronization input to the synchronization input 27 of the block 3 receives a synchronization pulse from the control output of the driver TS 1. The control output of the driver 1 is the output of a frequency divider, the input of which is connected to the output of a clock generator. The frequency of the pulses at this output of the driver 1 is sh times lower than the frequency at the clock output. When a pulse arrives at the synchronization input 27 of the block 3 for determining the sequence of extremums of the signal, the triggers are set to one.

5 22 of the first group and recording information from the outputs of the selector 24 to the triggers 23 of the second group. When a synchronization pulse arrives at the clock input of the selector 24 at its kth output

0 will signal 1 if K-and trigger 22 is in the one state and all triggers 22 with numbers less than K is in the zero state. As a result of the communication of the triggers 23 with

5 dami elements AND 19 code previously defined maximum is not taken into account when determining the maximum in the next cycle of the digital filter. Thus, in the second cycle of work

A digital filter 0 at the output of the SRI 20 element appears bitwise as the second-order code of the second statistic R2 - n-n-f ..., x). In the nth cycle of the digital filter at the element

OR 20, i.e. at the output of block 3, in

x).

0

is the code of the number K (x

those.

x signal accounts

n to-and h ° minimum sequence from

 five

to

From the code 3 block code, the code for the d order of the statistics R (+ tc tc bit (the high order bit) goes to the first input of the I 4, FTa element, the second input of the I 4 element) from the output of the ring shift register 5 enters the one bit code of the coefficient :(. Element And 4 implements a pull operation (w- "4 -. Xj., The serial code at the output of the element And 4 is converted into the corresponding. Parallel code at the output of the converter 6, which can be implemented as a shift register. The product code i, R (x ,,,..., X enters the information the input of accumulating adder 7. When the next reference arrives at information input 10 of digital fpter, the control pulse from control input 1 sets accumulating adder 7 to the zero state (adder is reset).

Thus, after n cycles of operation of the digital filter B, the accumulating adder 7 is generated binary.

code number

 -Y y

Multiplier

8 implements a code multiplication operation

the number of pa of the output of accumulating sum 7 to the code of the contents of block 9 of coefficient memory, i.e. per binary code value of the gain p.

Due to the possibility of implementing a rank filter 1 and signals, the proposed digital filter improves the filtering quality of noisy signals as compared to the known digital filters. For example, due to the possibility of implementing a median filtering of signals, this digital filter allows smoothing out impulsive noise well and not distorting a significantly useful signal. Using the proposed digital filter: other types of noise can also be smoothed, for example, white noise can be smoothed. no moving averaging.

Formula of Invention

 Digital filter containing memory block, AND element, accumulating the sum i iaaTop, memory block of coefficients,. form clock pulses and;) A multiplier, the first input of which is connected to the output of the memory block 5 "

0

five

In order to improve the accuracy of filtering noisy signals, a block is introduced: determining the sequence of signal extremes, ring shift: register and serial to parallel converter, the outputs of the memory block are connected to the corresponding information inputs of the block determining the sequence of signal extrema The output of which is connected to the first input of the element I, the second input of which is connected to the output of the annular shift reg: Istra, the output of the element AND is connected to: The information input of the serial code converter to the parallel code, the output of which is connected to the input of the accumulating adder, the second input of the multiplier is connected to the output of the accumulator of the adder, the output of which is the output of the digital filter, the clock output of the clock pulse generator is connected to the clock inputs of the code converter and the memory unit, and the output of the controls is connected to the synchronization inputs of the accumulating adder, the ring shift register and the block for determining the sequence of the ex the signal tremes, the setup inputs of the accumulator adder, the signal extremum sequence determination unit and the memory block are interconnected and are the control input of the digital filter, and the information input of the memory block is the information input of the digital output.

2 Фш1ьр under item 1, characterized in that the block for determining the sequence of extremes of the signal contains n elements And, where n I, 2, 3,.,. - order of a digital filter, n elements EXCLUSIVE OR,: and triggers of the first group, n triggers of the second group, the selector and the UTI element whose inputs are connected to the outputs of the SPs of the AND elements, the first inputs of which are 5v as the corresponding information inputs of the signal extremum sequence determination unit , and the second and third inputs of the elements And are connected respectively to the outputs of the n triggers of the first and second groups, the outputs of the elements And are connected to the first inputs of the elements EXCLUSIVE NL, the second inputs of which are connected to the output th element SHSH, B7

The output of the block for determining the signal extremum sequence, the outputs of the n elements are EXCLUSIVE OR are connected to the inputs of the installation in the O triggers of the first group, the output of the 1st of which (where i 1, π). connected to the i-M input of the selector, the i-th output of which is connected to the input of the installation in

About i-ro trigger second

J5

AT

groups, the inputs of the setup in 1 n triggers of the second group are combined with each other and are the installation input, and

the clock input of the selector and the inputs of the installation in 1 of the first group of flip-flops are interconnected and are the synchronization input of the signal determining unit of the signal sequence.

Editor M. Tovtin

fie.Z

Compiled by A. Osipovich

Tehred N. Bonkalo Proofreader 0. Lugov

Order 3927/58 Circulation 816 Subscription

. VNIIPI USSR State Committee

for inventions and discoveries N3035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

77

Claims (3)

1. A digital filter containing a memory block, an AND element, an accumulating adder, a coefficient memory block, • a clock generator and a multiplier, the first input of which is connected to the output of the signal coefficient memory block, a ring and a parallel-to-code code converter are connected! informational 1244786 4 cents, characterized in that, in order to increase the filtering accuracy of noisy signals, a shift extreme sequence determination block is introduced: register ι sequential: ny, block outputs · with corresponding inputs of the signal extreme sequence determination block, the output of which is connected to the first input of the And element , the second input of which is connected to the output of the annular shift register, the output of the element And is connected to the information input of the serial code to parallel code converter, the output One of which is connected to the input of the accumulating adder, the second input of the multiplier is connected to the output of the accumulating adder, the output of which is the output of a digital filter, the clock output of the pulse shaper is connected to the synchronization inputs of the code converter and the memory unit, and the control output is connected to the synchronization inputs of the accumulating adder, ring the shift register and the unit for determining the sequence of extrema of the signal, the installation inputs of the accumulating adder, the unit for determining the sequence The extrema of the signal and the memory block are interconnected and are the control input of the digital filter, and the information input of the memory block is the information input of the digital filter. 2 ^ '. Filter by π. 1, characterized in that the block for determining the sequence of signal extremes contains η elements And, where η = 1, 2, 3, ... is the order of the digital filter, η elements are EXCLUSIVE OR, η are triggers of the first group, η are triggers of the second group, selector and an OR element, whose inputs are connected to the outputs „η of AND elements, the first inputs of which are the corresponding information inputs of the unit for determining the sequence of signal extremes, and the second and third inputs” of AND elements are connected respectively to the outputs η of the triggers of the first and second g group, outputs η of AND elements are connected to the first inputs of EXCLUSIVE OR elements, the second inputs of which are connected to the output of the OR element, which is the output of the block for determining the sequence of signal extrema, the outputs η of the EXCLUSIVE OR elements are connected to the installation inputs of the first group of triggers, output i- ro of which (where i = 1 ,. η) is connected to the ith input of the selector, the ΐth output of which is connected to the installation input in О of the i-ro trigger of the second group, and the installation inputs of 1 η of triggers of the second group are connected between themselves are full-time input, and the clock input of the selector and 5 inputs of the installation in 1 triggers of the first group are interconnected and are the synchronization input of the unit for determining the sequence of extremums of the signal.