SU1376241A2 - Apparatus for digital support of recurrent signal phase - Google Patents

Abstract

The invention relates to electronics and provides an extension of the working frequency range. The device contains a pulse generator, an impulse accumulator, a measuring pulse counter, a periodic signal detector, a pulse counter, a memory register, and a parallel accumulator. To achieve the goal, And elements and a block for calculating the order of the output values of the pulse counter are introduced. The calculation unit is made in the form of three additional elements I. The counter of pulses 5 is made in the form of an additional-parallel accumulator adder. 1 hp F-Gla, 2 Il. (L

Description

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The invention relates to electronics, can be used in radio engineering, acoustic and electric systems to obtain information about the instantaneous current value of the phase of a periodic signal, in particular in terms of its frequency and phase modulation, and is an improvement of the device . St. No. 902266.

The goal is to expand the operating frequency range.

FIG. Figure 1 shows the electrical circuit diagram of a digital tracking device for a periodic signal phase; in fig. 2 - timing charts of the device. The digital phase tracking device of a periodic signal contains a generator of I pulses, an adder 2 pulse sequences, a measuring counter 3, a detector of 4 zeros of a periodic signal, a counter of 5 pulses executed in the form of an additional parallel accumulator accumulator, a memory register 6, a parallel accumulator accumulator 7 , elements 8 and 8, calculating the order of the values of the output signal of the measuring pulse counter, made in the form of the first 10, second 11 and third 12 additional I. elements

The generator 1 contains the master oscillator 13, 1-K-trigger 14, the first 15, the second 16, the third 17 and the fourth 18 AND elements.

The detector 4 contains the shift register 19, the fifth 20, the sixth 21, the seventh 22, and the eighth 23 AND-NOT elements. Counter 3 contains the first 24 and second 25 four-bit counters Parallel accumulator-accumulator 7 contains the first 26 and second 27 parallel four-digit adders, as well as the first 28 and second 29 four-digit registers.

The adder 2 of the pulse sequences contains the ninth 39 and tenth 31 NAND elements.

The output pulse counter 5, made in the form of a parallel accumulator accumulator, contains the third 32 and the fourth 33 parallel four-bit adders, the third 34 and the fourth 35 four-digit registers, as well as the fifth - twelfth 36-43 inverters.

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The device works as follows.

A periodic signal arrives at the device input, the frequency of which is close to the lower limit of the frequency range, i.e. approximately equal to, for example, 16 kHz (Fig. 2a, interval). In this case, the duration of the peri ode is close to maximum. Detector 4 zeros at the signal transition through zero from - to + produces two pulses separated in time, the first pulse (Fig. 26) fixing the zero phase value, and the second pulse (Fig. 2c) is shifted relative to the first, these pulses are synchronized with the first one and the second clock of the generator 1, whose frequency is equal, for example, 4 MHz. Moreover, the first impulse is formed at the output of the eighth element AND-NO 23, and the second impulse at the output of the sixth element AND-NOT 21.

On the first pulse, the contents of meter 3 are recorded in memory register 6. At the same time, with this pulse, the counter 5 and the parallel accumulator 7 are set to the initial, in this case, zero state. Thus, at this moment, the contents of counter 5 correspond to the zero value of the phase of the periodic signal, and the number at its output corresponds to this value.

By the second pulse, the contents of the measuring counter 3 is set to the initial one state,

In the intervals between the pulses of the installation through the counting input, the counter 3 is filled with pulses of frequency F, coming from the output of the fourth AND-HE element 18 (MHz). As a result, at its output a number is formed equal to the number of incoming pulses, but in reverse

de, i.e. counter 3 works on subtraction. For the period T of the input signal, the measuring counter 3 receives FxT pulses. In register 6, the number from counter 3 is written in reverse code

DZ S - F-T,

where S is the capacitance of the counter 3.

Since in the lower part of the tracking range (with fy) the period T is closer to its maximum value, the input of counter 3 receives a glint to the maximum number of pulses of the clock frequency F. Consequently, at the end of the period T in counter 3 there is a number close to zero . This number is recorded in 6 memory registers.

From the output of register 6 of memory, the code of the most significant bits is simultaneously applied to the input of the parallel adder of accumulator 7 and to the input of block 9 of calculation.

Block 9 works as follows.

All bits of register 6 are set to 1, in this case, the outputs of block 9 are also set to 1.

The forward outputs of block 9 are connected to the inputs of the lower bits of the parallel accumulator adder 7 in reverse order, i.e. the highest bit is included at the input of the first (low) bit, (n-1) th - at the input of the second bit, etc. As a result, when the value of outputs 1, at the time of each gate from the output of the tenth element, AND-NOT 31 from the matrix 2, the parallel input of the higher bits (the inputs of the fourth parallel four-bit adder 33) are summed by O and 1 at the transfer input of the fourth parallel four-digit adder adder 33.

The 1 transfer is formed by the existence of all 1 at the inputs of the third parallel four-bit adder 32 and the constant 1 at the transfer input PO. As a result, the counter 5 pulses, in the case of all 1 at the input of block 9, works

in four-bit pulse counter mode.

The low-order bit at output 1 of register 6 is O, the remaining bits are 1. In this case, the outputs of block 9 are 1, and the output of the third additional element is 12 O. At the time of each gate in the pulse counter 5 O, the fourth input is parallel parallel four-bit adder 33, and one of the inputs of the third parallel four-bit adder 32 and 1 along the transfer output from the third bit to the fourth of the third parallel four-bit adder 32. This 1 forms 10

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c due to the existence of all 1 at the inputs of the third parallel four-bit adder 32 and 1 at the entrance of its transfer. As a result, the pulse counter 5 in this case operates in the five-bit pulse counter mode.

The second bit at the output of register 6 is O, the rest 1. In this case, the outputs of the second 11 and third 12 additional elements And have the value O. The counter 5 is impu, tsov works in the mode of the six-digit counter of impulses.

The third bit at the output of register 6 is O. In this case, the additional elements And 0, 11 and 12 outputs O, Counter 5 im-. pulses operate in a seven-bit pulse counter mode.

The fourth bit of registers 6 is O. In this case, the outputs of block 9 are O. Counter 6 pulses operates in the eight-bit counter pulses.

Thus, in the case of the very ding period T, when at the output of the fourth bit of register 6 exists O, the counter 5 operates in the mode of the eight-bit binary pulse counter. At the same time, due to the presence of all 1 on the inverse outputs of block 9, all elements of AND 8 open. The inputs of these keys are connected to the outputs of the last four most significant bits of the parallel accumulator-accumulator 7, and the outputs of the keys to the inputs of its corresponding bits.

With the inclusion of all elements And 8; All eight bits of the parallel accumulator accumulator have feedback from the outputs to the inputs of the second term and, thus, all bits of the parallel accumulator accumulator are switched on in the parallel accumulator accumulator mode.

As a result, at frequencies of the input signal close to f, all eight bits of measuring counter 3, counter 5 and parallel accumulator 7 participate in device operation.

In this case, the frequency pulses F from the output of the second element AND-NOT 16 of the Generator 1 are fed to the input of the adder 2 and then to the counting input

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counter 5 pulses. At the same time, these pulses from the output of the adder 2 arrive at the input of the gating of the parallel adder-accumulator 7, to the parallel input of which from the register 6 the misalignment of the LZ is applied. Consequently, with each frequency pulse F, the accumulated amount in the parallel accumulator 7 is increased by & S. With continuous gating parallel accumulator drive 7 overflow

is produced at its output

taking into account the fact that l8,.

& S

The total number of overflow cycles of the parallel accumulator accumulator 7 for the period of the input signal T

ten

K J tl5

Thus, the input of the adder 2 and further to the counting input of the counter 5 for the period of the accompanied signal T receive additional them

the pulse, and the cycle of filling the pulses, which is equal to the value of the mismatch. The transfer pulse enters the input of the ninth element AND-NOT 30 of the adder 2, where it is gated with the pulse of the second clock of the generator 1, which arrives at the second input of the ninth element of the AND-NOT 30. As a result, the output of the adder 2 forms an additional pulse synchronized with the second clock of the generator 1, which is fed to the counting input of the counter 5 pulses and gating the input of the parallel accumulator 7.

Thus, at the moment of the overflow of the parallel accumulator-accumulator 7, the initial sum is entered into it, and is equal to B, which is the initial one during the subsequent cycle of its filling. If there is a residue in the parallel accumulator 7 at the time of the formation of the overflow pulse, the initial value is the sum of the remainder and JS (later to simplify the understanding of the operation of the circuit, the description is given without considering the remainder).

Number of pulses, strobing parallel accumulator ad- Tel 7 in the next accumulation cycle is equal to

20

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thirty

35

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in the measuring counter 3. The total number of pulses received at the counting input of the counter 5 pulses during the period T of the input signal is equal to

N

T-F + + iS

and does not depend on the magnitude of this period and frequency at the steady-state frequency of the input signal (in the case of the eight-bit device N 2 under consideration).

Thus, at the output of the device, a digital scan is formed with a constant number of discretes during the period of the input signal, i.e. synchronized with the beginning and end of this period. The instantaneous values of this sweep correspond to the current values of the phase of the input signal with an error not exceeding one sampling of the counter of 3 pulses (Fig. 2a, until time t,).

In the second case, at the input of the device at the moment of time t (Fig. 2a) the frequency of the input signal abruptly increases by 3.5 times. In this case, the senior (eighth) bit of the measuring counter 3 pulses remains in state 1, the previous seventh bit takes the zero value.

P

ent

rs-dsi

where is ent

- the whole part of the expression in brackets;

(S-flS) is the capacity of the parallel zsgm storage tank 7 after the introduction of the initial number 4 S.

The filling period of the parallel accumulator 7 is

X -. as F

in the measuring counter 3. The total number of pulses received at the counting input of the counter 5 pulses during the period T of the input signal is equal to

N

T-F + + iS

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j

and does not depend on the magnitude of this period and frequency at the steady-state frequency of the input signal (in the case of the eight-bit device N 2 under consideration).

Thus, at the output of the device, a digital scan is formed with a constant number of discretes during the period of the input signal, i.e. synchronized with the beginning and end of this period. The instantaneous values of this sweep correspond to the current values of the phase of the input signal with an error not exceeding one sampling of the counter of 3 pulses (Fig. 2a, until time t,).

In the second case, at the input of the device at the moment of time t (Fig. 2a) the frequency of the input signal abruptly increases by 3.5 times. In this case, the senior (eighth) bit of the measuring counter 3 pulses remains in state 1, the previous seventh bit takes the zero value.

With the value of the seventh bit O, and the eighth 1 measuring counter 3 pulses and register 6, the signals from the outputs of block 9 convert the counter 5 pulses from eight-bit to seven-bit.

At the same time, the inverse signal from the output of the first block 9 closes one of the elements And 8 and breaks the feedback of the eighth bit of the parallel accumulator 7.

A zero is applied to the first input of the second parallel four-bit adder 27. As a result, the most significant bit of the parallel accumulator adder 7 stops working in the signal accumulation mode. But, since there is 1 at the second input of the second parallel four-bit adder 27, corresponding to the value of the highest bit of register 6, it works in the transfer translation mode from the previous seventh bit directly at the transfer output. Therefore, the parallel adder-5-bit adder 26 of the direct transponder 7 is converted to a seven-bit.

Thus, the mutual correspondence between the number of functioning bits of the measuring counter 3 pulses, the parallel accumulator 7 and the counter 5 pulses is preserved. When the frequency of the input signal is 3 ,, the device functions as a seven-bit one, and switching it from eight-bit mode to seven-bit mode is performed by the And 8 element and the block 9.

Let the frequency of the input signal change 3.5 times in a jump-like manner from time t (Fig. 2a). At time t, t ,, t, its phase is zero. FIG. 21 shows the ideal phase values of this signal; FIG. 2D - phase count at the output of the four higher bits of the device. The speed of the device is equal to the period of the input signal. Therefore, from the moment of the frequency hopping of the input signal t to the end of the first period of the modified frequency t, the output signal is distorted.

But already from the moment of time tj, i.e. With a delay for the period of the input signal, the digital phase tracking is carried out within the limits of the required accuracy of the device.

Consider the operation of the device in the case of f „„ (. L 16 f ,. As in the pre

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In the previous case, the actual resolution of the computational part of the device decreases with increasing input signal. In this case, the value of the period of the input signal is minimal. Therefore, already the four most senior 55 bits of the measuring counter of 3 pulses do not change their initial state, and their value

merged through the fifth, sixth, seventh and eighth bits to the output of the second parallel four-bit adder 27 and the parallel adder drive 7 operates in four-bit mode. As a result, the device performs digital tracking of the phase of the periodic signal, whose frequency is in four-bit mode with an accuracy of the fourth binary bit.

There are two features of the operation of the device.

The transfer input of the low bit of the parallel accumulator 7 is constantly fed 1, compensating for the loss of 1 when d8 is formed by the counter result pulse counting code 3.

At the moment of the beginning of each tracking cycle, one pulse is added to the Counter 5 pulses through the ninth 30 and tenth 31 elements of AND-NOT. This pulse compensates for the inaccuracy of the digital phase tracking, which is due to the fact that the beginning of the period by the detector 4 is always recorded with a slight delay.

Formula and -3 gain

1. A device for digital tracking of the phase of a periodic signal according to the author. St. 902266, characterized in that, in order to expand the working frequency range, elements AND and a calculator of the order of magnitude of the output signal of a pulse counter are introduced, and elements AND are connected between the outputs and the second inputs of the higher bits of the parallel accumulator, and the order of the magnitude of the measurement signal 62418

equals 1, i.e. all outputs of register 6 are set to 1. At all outputs of block 9, 1 is present, which switches the counter of 5 pulses to four-bit mode. At the same time, all zeros from the inverted outputs of block 9 exclude four higher 10 bits of the parallel accumulator 7 from the feedback elements. And since 1 is fed to the first inputs of these high bits, the transfer from the fourth bit output of the first parallel four-

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merged through the fifth, sixth, seventh and eighth bits to the output of the second parallel four-bit adder 27 and the parallel adder-drive 7 operates in four-bit mode. As a result, the device performs digital tracking of the phase of the periodic signal, whose frequency is in four-bit mode with an accuracy of the fourth binary bit.

There are two features of the operation of the device.

The input of the transfer of the lower bit of the parallel accumulator 7 is constantly fed 1, which compensates for the loss of 1 when d8 is formed by the inverse code of the result of the counting of pulses by the counter 3.

At the moment of the beginning of each tracking cycle, one pulse is added to the Counter 5 pulses through the ninth 30 and tenth 31 elements of AND-NOT. This pulse compensates for the inaccuracy of the digital phase tracking, which is due to the fact that the beginning of the period by the detector 4 is always recorded with a slight delay.

Formula and -3 gain

Claims (2)

1. A device for digital tracking of the phase of a periodic signal according to the author. St. 902266, characterized in that, in order to expand the working frequency range, elements AND and a calculator of the order of magnitude of the output signal of a pulse counter are introduced, and elements AND are connected between the outputs and the second inputs of the higher bits of the parallel accumulator, and the order of the magnitude of the signal of the measuring pulse counter is connected by inputs to the outputs of the memory register and inverse outputs to the second inputs of the elements AND, the outputs of the lower and upper digits of the calculation unit measuring a magnitude of the pulse counter output signal inputs connected sootvetstvennok senior and mladshihrazr rows pulse counter, vsholnennogo as additional parallel adder-accumulator. 2. The device according to claim 1, about tl and - that the block for calculating the order of magnitudes of the output signal of the measuring pulse counter is made in the form of serially connected additional elements AND, second. the inputs and outputs of which are the inputs and outputs of the calculator of the order of the values of the output signal of the measuring pulse counter. VdPoZ