SU1057891A2 - Device for measuring power of losses in thyristor switching - Google Patents

Abstract

DEVICE FOR MEASURING THE POWER OF LOSSES AT THE COMMUTATION OF TYRISTOBE by author. St. No. 960673, that is, in order to expand the measurement range and improve accuracy, a shift register, a zero bit binary code check block and a second coincidence circuit are entered into it, the shift register being connected between the outputs of the analog-to-digital converter and the inputs of the computational block, the inputs of the check block for zero bits of the binary code are connected in parallel to the information inputs of the shift register connected by a counting input to the output of the analog-to-digital converter's conversion, and the control its input is with the first output of the check block for zero bits of the binary code, which is connected by its second output to the control input of the matching voltage channel node, the third output to the first input of the second coincidence circuit, connected by its second input and output, respectively, to the output the synchronization node and the counting input of the number counter (L measurements, and the clock input of the check unit for zero bits of the binary code is connected to the control input of the analog-digital converter. ate 00 co

Description

The invention relates to the field of electrical measurements, and more specifically to devices for determining the parameters of semiconductor devices, specifically for measuring power and energy loss, which is 11 (it is on the thyristor when it is switched.

According to the main author. St. No. 960673, a device containing a test circuit with terminals for connecting the device under test is known, the generator outputs of the control current are connected to the first and second, the input of the voltage sensor is connected to the second and third, and the current sensor inputs are connected to the second and third terminals the outputs of the voltage and current sensors through the matching nodes of the voltage and current measurement channels are connected to the corresponding wiring blocks, the control inputs of which are connected to the output of the storage pulse shaper, and their outputs through an analog switch to serially connected analog-to-digital converter, computing unit and information output unit, a control circuit connected by its output to the control r, mm inputs of an analog switch and analog-digital converter, which is connected by an output of the conversion End to the input of the computing unit , startup and synchronization nodes, control unit in the storage and assembly. The control unit for sampling and storage is made in the form of a count of the number of measurements, a distribution block, a combination circuit, a clock count, a clock count, a coincidence circuit, a crystal oscillator, a last clock selection circuit, and a first pulse separation circuit; with the output of the startup node by a counting input with an output of nodes, a synchronization clock, to which the control inputs of the distribution block and the extraction circuit of the first pulse are also connected, and the outputs of the counter chi The measurements are weakly distributed through the distribution block, one of the outputs of which is connected to the synchronization node, connected to the inputs of the clock de-insulator, to which are also connected the outputs of the number of cycles and connected in parallel with the inputs of the last clock selection circuit, the output of which is connected to one of the circuit inputs a coincidence connected by another input with the output of the crystal oscillator and the second input of the first pulse extraction circuit, and the output with the counting input of the clock number counter whose zero input is connected to the output In the extraction circuit of the first pulse connected to the inputs of the control current generator of the control i-circuit, the outputs of the clock decoder are connected via a combination circuit to the input of the storage pulse former 1.

A disadvantage of this device is the limited range of measured voltage signals, and the comparatively low accuracy in measuring instantaneous values of a voltage of small magnitude. When the thyristor is turned on, the voltage on it changes in time from several kilovolts to two or three volts, therefore the sampling-storage device, the analog switch and the analog-digital converter process signals that vary about a thousand times. Since the maximum value of the voltage with which these nodes operate is limited by their allowable input voltage, when processing instantaneous voltage values corresponding to the end of the transient, the error in measuring signals of small magnitude can be quite significant. In particular, if the conversion of the instantaneous values of an analog signal to a binary code is carried out by an analog C-digit converter with a 12-bit day output code (which is 2 4096 gradations), then when converting an input signal that is less than the maximum value 1000 times, the conversion error is rapid. one gradation is 25%. Increasing the number of bits of an analog-to-digital converter, more than 12, as is known, is a technically difficult task and dramatically reduces installation speed, since such analog-to-digital converters have a very long conversion time. Extending the dynamic range of the sampling-storage devices to 60 dB is also quite difficult, especially when considering the required speed.

The purpose of the invention is to expand the measurement zone and increase the accuracy of measurements.

This goal is achieved by the fact that the device for measuring the power loss during switching of the switching device contains a test circuit with terminals for connecting the device under test, the first and second of which are connected to the voltage sensor inputs of the second and third sensors, and The ontur and second terminals include the current sensor strokes, the outputs of the voltage and current sensors through the matching nodes of the voltage and current measurement channels are connected to the corresponding sampling-storage units, controlling e inputs of which are connected to the output of the storage pulse generator, and their outputs through an analog switch to series-connected analog-to-digital converter, computing unit and information output unit, a control circuit connected by its output to control inputs of an analog switch and analog-to-digital converter which is connected by the output of the conversion to the input of the computing unit, the start and synchronization nodes, the sample and storage control unit, which is designed as a counter the number of number of measurements, the distribution block of the combining circuit, the decoder of the takg, the counter of the number of clock cycles, the coincidence circuit, the crystal oscillator,. :: last clock cycle and the first pulse.. - pulse pattern for selecting the first pulse are connected to the output of the trigger node the counting input of the output of the synchronization node, which is also connected to the control inputs of the distribution block and the first pulse output circuit, and the outputs of the counter of the number of measurements through the distribution block, one of the cat outputs cerned is connected with the synchronization node podklyuchenyk inputs of decoder cycles to kotoryg. There are also connected the number of clock counts and connected in parallel to the inputs of the last clock circuit, the output of which is connected to one of the inputs of the coincidence circuit connected by another input to the output of the quartz oscillator and the second input of the first pulse extraction circuit, and the output to the counter input of the counter the number of ticks, the input of the zero setting of which is connected to the output of the extraction circuit of the first pulse connected to the inputs of the control current generator, and the control circuit; the outputs of the clock pulse tuner are connected via the circuits combining to the input of the storage pulse generator, a shift register, a zero bit binary code check block and a second match circuit are entered, the shift register is connected between the outputs of the analog-digital converter and the inputs of the computing unit, the binary code block inputs are connected in parallel to the information inputs of the shift register connected by the counting input to the B1-1 input. The conversion end of the analog-digital converter and the control input - to the pe output of the checking unit. whether bits of a binary code, which is connected by its second output to the control input of the matching node of the voltage measurement channel, by the third output to the first input of the second coincidence circuit, connected by its second input and output, respectively, to the output of the synchronization node and the counting input of the measurement number counter, and the clock input of the checking unit is on. zero bits of the binary code is connected to the control of the analog-to-digital converter input.

In the drawing. The block diagram of the proposed device.

The device contains a test circuit 1, to the output terminals of which through the current sensor 2 are connected terminals for connecting the power terminals of the device under test (thyristor) 3 and voltage sensor 4, To the terminals for connecting the control terminals of the test device 3, an output of & 1 generator 5 control current. The outputs of the current and voltage sensors 2 and 4 are connected to the inputs of the securing node 6 and 7 measurement channels of the voltage and current, the outputs of which are connected to the inputs of the .8 and 9 blocks of sampling-storage, the control inputs associated with the output of the driver 10 impulses storage. The outputs of the storage-storage units 8 and 9 are connected via analog switch 11 to the input of analog-digital converter 12 (ADC), and the outputs of ADC 12 are connected to the inputs of the binary check block 13 and through the shift register 14 to the inputs of the computing unit 15 associated with block 16 output information. Output The conversion end of the A / D converter 12 is connected to the counting input of the shift register 14 and to the input of the computing unit 15. The output of the synchronization unit 17 is connected to the input of the distribution unit 18, one of the inputs of the first pulse separation circuit 19 and one of the inputs of the second coincidence circuit 20, the other input of which connected to the third output of the block 13 for checking zero bits of the binary code, the second output of which is connected to the control inputs of the matching node 7 of the voltage measurement channel, and the first output to the control input of the shift register 14 . The output of the second coincidence circuit 20 is connected with the counting input of the counter 21 of the measurements, the input of which is set to zero is connected to the output of the start node 22, and the clock to the inputs of the distribution unit 18, the outputs of the latter are connected to one group of inputs of the de-diffractor 23 cycles, - which is connected to the number of clock counts 24 and to the inputs of the last clock allocation circuit 25. The output of the clock selection circuit 25 is associated with one of the inputs. There is a first coincidence circuit 26, in a swarm whose input is connected to the output of a quartz oscillator 27 and the second input of the extraction circuit 19 of the first pulse, and the output to the counting input of the counter 24 in the number of ticks. The output of the extraction circuit 19 of the first pulse is connected to the input of the control current generator 5, to the zero-setting counter of the number of cycles 24 and to the input of the control circuit 28 by the analog switch 11 and the ADC 12. The decoder outputs 23 clock pulses connected to the inputs of the combining circuit 29, the output of which is connected to the input of the shaper 10 pulses of storage. The installation input of the synchronization unit 17 is connected to the last output of the distribution unit 18. The device works as follows. A voltage is applied to test device 3 from test circuit 1, the value of which is determined by the test conditions. When a triggering pulse appears at the input of the control current generator 5, the latter generates a control current pulse of a given shape and amplitude through the control transition of the test device 3. When this thyristor 3 turns on, the voltage across it drops from a value equal to that applied before switching on to several volt, and the pulse of the anode current passes through the device, the rise rate of which, the amplitude and duration are determined by the parameters of the test circuit 1. The power loss during switching is defined as the product instantaneous values of the anode current and voltage on the test thyristor 3 at each time point. From the outputs of the sensors 2 and 4 of the current and voltage, through the matching nodes 6 and 7, the time-varying voltage levels proportional to the current through the device under test 3 are applied to the inputs of the sampling-storage units 8 and 9. A pulse is output from the output of the storage pulse generator 10 to the control inputs of block 8 and 9 of the sample-store. The process of turning on the test device occurs periodically, for example, at a frequency of 50 Hz. With each subsequent switching on of the tested thyristor 3, the front edge of the storage pulse shifts from the beginning of the control current pulse by the value of KAt, where K is the number of made inclusions, and At is the sampling step, i.e. time between two adjacent points of the input current or voltage signal), which will be measured by the device. Before the storage pulse arrives at the outputs of blocks 8 and 9, the sampling-storage voltage at each time instant is equal to the voltage at the input of the block. With the arrival of the front (the front of the storage pulse, the voltage at the output of blocks 8 and 9 ceases to change and until the rear edge of the storage pulse arrives, it remains constant and equal to the value of the voltage at the input of the block at the time of the arrival of the leading edge of the storage pulse. Since the front edge of the storage pulse with each subsequent switching on of the test thyristor 3 is shifted relative to the beginning of the control current pulse by the value of Ut, then the outputs of the blocks 8 and 9 of the sample-storage sequentially appear voltage levels proportional to respectively, the instantaneous values of the current and voltage on the thyristor 3 at times O, 1 fct, 2ut, 3 & t, ..., etc., to M & 1, where N is the number of measurement points set before the test began. The switch 11 connects the input of the A / D converter 12 to the outputs of the sampling-storage units 8 and 9. The A / D converter 12, with the arrival of a start pulse from the control circuit 28, converts the voltage levels that come to its input into a digital code fed to the information inputs of the register 14 the shift and input of block 13 checks for zero bits of a binary code. The latter analyzes the higher bits of the ADC output code. Further operation of the installation will be considered at the beginning when converting analog quantities of a sufficiently large value. At the same time, in the star1L1X bits of the output code of the A / D converter 12 there are levels of logical Iu. The signal from control output 28, which arrives at the control input of block 13 for checking zero bits, serves to determine whether this code at the output of A / D converter 12 belongs to instantaneous current values , or to data on instantaneous: values of voltage. If in the higher bits of the output code of the A / D converter 12, when analyzing the voltage data, the logic level 1 is present, then the first and second outputs of the block 13 for checking zero bits appear to be a zero code, at which the change of the transmission coefficient in the matching node 7 does not occur the output code is transmitted to the computing unit 15 via the shift register 14 without shifting the information in the latter. The binary code is received in the memory of the computing unit 16 when the signal at the output of the A / D converter 12 is received. The conversion end also serves as a clock when writing information to the offset register 14. After writing to the computing unit 15 a pair of binary numbers corresponding to the instantaneous values of current and voltage at a given time, they are multiplied and fed to the memory of the computing unit 15. Then, when the next control current pulse is applied, the measurement process is repeated for the next point, i.e. next point in time.

The formation of the leading edge of the storage pulse, its shift from one switch to the next by a given value, the synchronization of this front with the start pulse of the control current generator 5 occurs as follows.

When the number of measurements from the start-up node 22 arrives at the zero input of the counter 21, all the triggers of the counter 21 are set to zero. If a binary number has arrived at the input of block 13 for checking for zero bits of a binary code and has logic levels 1 in the higher bits, then the third output of block 13 is a logic level 1 arriving at one of the inputs of the second coincidence circuit 20. Then, the counting input of the counter 21, the measurements of the output of the second coincidence circuit 20, begins to receive pulses from the synchronization node 17, arriving at the second input of the coincidence circuit 20 and setting the switching frequency of the test device (most often 1 or 50 Hz are used). When each next pulse arrives, the trigger 21 of the counter 21 records a code, for example, a binary one, corresponding to the number of arriving pulses. This code from the outputs of the counter 21 of the number of measurements goes to the inputs of the distribution unit 18 together with the signal from the output of the node 17 of synchronization. Distribution unit 18 can be executed either as a decoder, or as a sequential register, and generates at one of its outputs, the number of which is equal to the number of measurements (sampling points), the level of logical

whereas on the rest

logical level O is present. The number of the output at which you generate 1 is equal to the number of 21 pulses recorded in the counter. For example, when recording twelve pulses j received from the synchronization node 17, only at the twelfth output of the distribution block 18, the logical level 1 is present. 65

The pulses from the output of the synchronization unit 17 also go to one of the inputs of the first pulse extraction circuit 19, to the second input of which comes a sequence of pulses from the output of the quartz oscillator 27 operating in continuous mode. The period of these pulses is equal to the interval between the points at which instantaneous values of current and voltage are measured (sampling interval). When each pulse arrives from the synchronization unit 17, a single pulse appears at the output of the extraction circuit 19 of the first pulse, the leading and trailing edges of which coincide with the corresponding edges of one of the output pulses of the crystal oscillator 27 and fall between the edges of the pulse that came from the output of node 17 sync. The pulse from the output of the circuit 19 of the extraction of the first pulse is fed to the input of the control current generator 5, start it and determine the beginning of the control current pulse of the test instrument. A pulse from the output of the extraction circuit 19 of the first pulse is set to the zero of the trigger 24 of the number of ticks. At the same time, from the output of the last clock cycle 25, one of the inputs of the first coincidence circuit 26 is supplied with a logic level 1 and the output frequency pulses of the crystal oscillator 27 arriving at its second input begin to pass to the counting input of the clock 24 times. When the code corresponding to the number of the last measurement point is recorded, a logic level O is formed at the output 25 of the last clock selection, and the flow of pulses to the counting input of the counter 24 of the number of clock cycles stops before the next pulse arrives from the synchronization node 17. Thus, with the arrival of each pulse from the synchronization node 17 and, accordingly, a change in the total counter 21 of the number of measurements per unit in the counter 24 of the number of clock cycles, the codes successively change from zero to maximum corresponding to the number of the last measurement point. The outputs of all the triggers of the counter 21 of the number of cycles go to one group of inputs of the decoder of cycles 23, the second group of inputs of which receive the outputs of the distribution unit 18. The decoder of cycles 23 forms a pulse at one of its outputs, and for each synchronization pulse a pulse will be generated at that decoder output 23, the number of which is equal to the number of synchronization pulses from the beginning of the measurement cycle. With

The arrival of each next synchronization pulse to the counter 21 of the number of measurements, level 1 appears at the next output of the distribution unit 18 and a pulse is generated at the next output of the decoder 23 clocks. All the outputs of the 23 clock decoder are connected to the inputs of the combining circuit 29, the output of which each time the test thyristor 3 is turned on will produce a pulse, the leading edge of which, each time it turns on, shifts from the beginning of the thyristor control pulse 3 by an amount t equal to the pulse duration at the output a quartz oscillator 27. These pulses are supplied through the storage pulse shaper 10 to the inputs of the sample-hold blocks.

Since when the thyristor 3 is turned on, the voltage drop across it monotonously decreases with time, when serially converting to digital code the points on the voltage curve in the higher bits of the output code of the ADC 12 will begin to appear participate block

If the bits of the binary code are zeroed, for example, in all three higher bits of the output code of the CPU 12 when measuring the point with the number K in tc, the levels are logical O, then the second output of the unit 13 turns on a control signal, for example, three-digit binary code

by which the transmission coefficient of the matching node 7 will double. At the third output of block 13, the logic level O is detected, which is fed to the input of the second coincidence circuit 20, and when the next synchronization pulse appears, the contents of the measurement number counter 21 will not change. Therefore, the shift of the leading edge of the storage pulse will be the same as in the previous cycle, and the point with the number K will be measured again, but the instantaneous value of the voltage at the Kth point, which is stored by the sample-storage device 9 and generated in binary the code will be twice as large. Upon completion of the conversion to binary code, the number is written to shift register 14. In order for the computational unit 15 to receive all the information in one scale, the unit 13 in this case generates a control command on the first output and the contents in the register

The shift will be shifted one bit toward the least significant bit. Then the information is transmitted to the high frequency numeral 15, the measurement of the point with the number K + 1 will immediately be conducted with a gain factor equal to 2, the level 1 being fed to the input of the second coincidence circuit 20, after converting the number to binary code information will also be shifted for one bit d.

If in the future at the K + P point the level of logical O returns to the three highest bits of the output ADC code, then the second output of the block 13 shows the command, increasing the c-transfer coefficient of the matching node 7 by 2 times, at the third output by Vits level O and K + P - point will be measured one more time. After the binary number is written to the register: the gistr of the 14th gate, a command appears at the first output of block 13, according to which the information in the register is shifted: two bits in the direction of the least significant bit.

With a further decrease in voltage drop: a double increase is also possible: the transmission coefficient of matching node 7. In this case, the first output of the zero-checking block 13 of the binary code will form a command for which the number recorded. In register 14 of shift, is shifted three bits in the direction of the least significant bit.

After measuring the last point on the voltage and current curves at the last output of the distribution block; and 18 appears at logic level 1, synchronization node 17 stops and the process is formed. The shift pulses are completed before the next pulse arrives from start node 22.

The proposed device allows improving the accuracy of measuring instantaneous power losses and expanding the range of measured values, which is especially important when measuring power losses when high-voltage modern thyristors are turned on, by introducing a binary code, shift register, second circuit into the device. matches and connections between them, which, in turn, allows the instantaneous values of the voltage drop to be converted to binary code at virtually any dynamic range. this does not change the voltage and ensures the required measurement accuracy in the whole dynamic range. At the same time, the required accuracy of measurements can be achieved using an ADC with a relatively small number of bits of the output code. The increase in the number of ADC bits, as is known, requires considerable technical and economic costs, which negatively affects the cost of the installation as a whole. Register shift introduction

11 105789112

and arranging communication with a matching element that, by changing the coefficient by overstretching the voltage channel, allows you to give a matching node of 2.4.8 ... 2; in addition, you can simplify the task of inputting a binary number to return information to the computing unit, And since all the numbers are entered into it, the bits recorded in the shift scale register. This is related to m, ha information.

Claims (1)

DEVICE FOR MEASURING POWER LOSS DURING SWITCHING OF A TYRISTOR by ed. St. No. 960673, characterized in that, with the aim of expanding the range of measurements and improving accuracy, introduced into it. a shift register, a unit for checking for zero bits of a binary code and a second coincidence circuit, the shift register being included between the outputs of the analog-to-digital converter and inputs of the computing unit, the inputs of the unit for checking for zero bits of a binary code are connected in parallel with the information inputs of a shift register connected by a counting input to the output The end of the conversion of the analog-to-digital converter, and the control input - with the first output of the check unit for zero bits of the binary code, which is connected by its second output m to the control input of the matching node of the voltage measurement channel, the third output to the first input of the second coincidence circuit connected to its second input and output, respectively, with the output of the synchronization node and the counting input of the counter of the number of measurements, and the clock input of the check unit for zero bits of the binary code is connected to the control input of the body. analog to digital conversion 1Sh. 25}