SU1580564A1 - Device for detecting errors in equal-weight code - Google Patents

Abstract

This invention relates to automation and computing. Its use in digital information processing systems allows for improved performance. The device contains a clock pulse generator 1, a multichannel pre-processor 2 parallel code in a pulse sequence, trigger 3, pulse counting unit 4, elements OR 5, 11, reversible drives 6, group of elements AND 7 and elements AND 9, 10. The goal is achieved by introducing groups of elements OR 8 and groups of elements And 12. 1 Il.

Description

The invention relates to automation and computer technology and can be used in digital information processing systems.

The purpose of the invention is improving performance.

The drawing shows a functional diagram of the proposed device.

The device comprises a clock pulse generator 1, a multi-channel converter 2 of a parallel code in a pulse sequence, a trigger 3, a pulse counting unit 4, a first element OR 5, reversible drives 6, a first group of elements AND 7, a group of elements OR 8, the first 9 and second 10 elements AND , the second! OR element 11 and the second group of AND elements 12. The device also contains information 13 and installation 14 inputs, information output 15 and output 16 of the end of work.

The device is designed to work with η-bit code with a constant number of K units.

Multichannel converter 2 can be performed on a pulse distributor, the outputs of which are connected to the first inputs of 2p groups of elements And (2p is the number of channels of converter 2), the second inputs of elements And of each group are information inputs 13 of the corresponding channel of converter 2, and the outputs are connected with the inputs of the OR element, the output of which is the output of the corresponding channel of the converter 2, the clock input of the pulse distributor is the clock input of the converter 2, and the output of its last discharge is the output converter end home 2.

The multi-channel converter 2 can also be made in the form of 2p shift registers connected by information inputs with the corresponding information inputs 13 of the converter 2, clock inputs with its clock input, and transfer outputs with the corresponding information outputs of the converter 2, the inverse outputs of each shift register are connected to the inputs its element And, and the outputs of the latter - with the inputs of the element And, the output of which is the output of the end of the Converter 2.

Trigger 3 is executed in the form of an RS trigger, if the multichannel converter 2 is executed on shift registers, or on a pulse distributor, the signal at the output of the end of operation of which is synchronized with a pause between clock pulses, or in the form of a counting trigger, if converter 2 is executed on a pulse distributor, a signal at the output of the end of which is synchronized with a clock pulse.

The reversible drive 6 can be made in the form of a reversible counter with two counting inputs to the bits, connected by direct outputs to the inputs of the OR element, the direct output of which is the first, and the inverse output is the second outputs of the drive 6, summing and subtracting the counting inputs of the counter are respectively the first and the second counting inputs of the reversing drive 6.

In the initial state, the code of the reverse drive 6, i from the inputs 14.i is written the code of the number n ^ ^ / inputs (p + i) -ro of the channel of the multi-channel converter 2.

Block 4 counting pulses can be made in the form of a reversible counter on b-] log _z (K ^? +2) L, K '= max (K, J ^ £) digits, summing and subtracting the counting inputs of which are respectively the first and second the counting inputs of block 4. The direct output of the high-order bit of the counter is the overflow output of block 4, and its outputs are connected to the inputs of the element And, the output of which is the information output of the counting block 4, and the element And is connected by inputs to the direct outputs of the bits of the counter with numbers equal to the numbers of units bits in binary the presentation of q + K, and the inverse of by the moves of the rest of its digits, where ς = 2θ “ ⁽ -K-10. In the initial state, the code of the number n ^ p + q is written to the counter of block 4 from inputs 14.p.

In addition, the reversible counter can be installed in the initial state from the inputs 14.p to the state in which the code of the number p-2p is written into it, i.e. q = 0, however, the overflow output of block 4 is the output of the threshold element with the weights of the inputs 2 ⁴ and the threshold K + 1 connected by the 5th inputs with the direct outputs of the reversible counter.

Elements And 12 can be installed directly on the outputs of the channels of the Converter 2.

The device operates as follows.

In the initial state, the multi-channel converter 2, trigger 3, drives 6 and block 4 are reset. A controlled code is supplied to the information inputs 13, and it is sent in direct form to the inputs of the channels from the first to the r-th, and to the inputs of the channels from the (p + 1) th to the (2 p) -th in inverse or in direct, but is inverted by installing inverters on the corresponding inputs of the multi-channel converter 2 or by performing the corresponding inputs of the converter 2 inverted.

When clock pulses arrive at the clock input of the multi-channel converter 2 from the output of the clock generator 1, converter 2 converts the number of unit signals at the channel information inputs from the first to the rth and the number of zero signals at the channel information inputs from the (p + 1) th to ( 2p) th in the number of pulses at the outputs of the corresponding channels. The pulses from the output of the (2p) channel of the multichannel converter 2 are fed to the subtracting counting input of block 4, and the pulses of the output of the rth channel are transmitted through the OR 5 element to the summing input of block 4. If the pulse arrives only to the summing or subtracting inputs of the block 4, then one is added to its contents, or one is subtracted from its contents, respectively. Pulses from the output of the i-ro channel of the multi-channel 'converter 2 are fed to the summing input of the reversing drive 6.1, and the output of the (p + i) -ro channel to the subtracting counting input reverse 6.i drive through the element OR 8.i. If the pulse is supplied only to the summing input of the reversing drive 6, then one is added to its contents, and if only to the subtracting counting input, one is subtracted from its contents. If pulses arrive simultaneously from the i-ro and (p + i) -ro or p-th and (2p) -th channels of the converter 2, then the state of the reverse to the accumulator 6.i or the counting unit 4 does not change due to the And elements 12.

The work is continued in this way _from before the end of the conversion of the input code by the multi-channel converter 2. Upon completion of the conversion, it is self-blocking and then does not generate pulses at the outputs of its channels.

In this case, the signal from its output of the end of operation of the converter 2 switches the trigger 3, the output of which appears a single signal. ' Next, the process of sequentially recalculating the contents ιό of reverse drives 6 to block 4 takes place. Let

6.1 - the smallest number of the reversing drive into which a nonzero code is recorded, and by the time the converter 2 is finished, each reverse drive 6.1 has a code for the number of individual signals on a pair of groups of information inputs 13.1 and 13. (p + i). In this case, a single signal C from the first output of the reversing drive 6.1 and single signals from the second outputs of the reversing drives 6.1 - 6. (i-1) allowed the passage of clock pulses through 30 element And 7.i and element IZH 5 to the summing input of the counting unit 4 and through element AND 7.i and element OR 8.1, the subtracting yield of the reversible drive 6.i _{s is} added each time to the contents of block 4, and from the contents of the reversible drive

6.1 unit is deducted. The work continues in this way until the reversible drive 6.1 is reset to zero, with a zero signal appearing at its first output 40, prohibiting the further passage of clock pulses through the AND 7.1 element, and at the second output, a single one, allowing them to pass through the AND 7. (1+ 1) -7. (p-1). And then, in the same way, the reversible drives 6. (i + 1) - 6. (p-1) are reset and their contents are converted to the block counter 4.

,

If the operation of device1 = 1 va continues until all reversible drives 6 are reset to zero, at the same time, on their second outputs, single signals appear at the inputs of the And 9 element and cause a single signal at output 16 of the end of the device, indicating the end of the operation cycle. Result

Ί η is removed from output 15: if X ₍ = K, then output 15 is a single signal, βοή η is 2 [X; “tK, then zero. If X;? T“ Ί 1 - 1

G, then the operation of the device continues until an impulse is accumulated in block 4 (K + 1), and a single signal appears at its overflow output, which passes through the And 10 element to the input of the OR element 11 and causes a single signal at the output 16 of the end of the device. Output 15 is a zero signal.

Thus, the proposed mouth; swarm provides higher; performance than known.

Claims (1)

Claim Device for detecting errors: in an equilibrium code containing a multi-channel parallel code converter in a pulse sequence, the information inputs of the first and second channels of which are the corresponding information inputs of the device, a clock pulse generator whose output is connected to the first inputs of the elements of the first group and the clock input of a multi-channel parallel converter (code in the pulse sequence, the output of which is connected to the trigger input, the output to which is connected to the second inputs of the AND elements of the first group and the first input of the first AND element, the first is the (p-1) -th reversible drives, the first outputs of which are connected to the third inputs of the same elements AND of the first group, the outputs of which are connected to the corresponding inputs of the first OR element , the second output of the i-ro reversible drive (i-1, p-1) is connected to the (i + +3) -th inputs of the (i + 1) -ro - (p-1) -th elements of the first group And (ϊ + 1) -μ the input of the first AND element, the output of which is connected to the first input of the second OR element, the output of which is the output of an eye the operation of the device, the pulse counting unit, the overflow output of which is connected to the first input of the second AND element, the output of the rth channel of the multichannel parallel code converter in the pulse sequence is connected to the rth input of the first OR element, characterized in that, in order to improve performance , the group of OR elements and the second group of AND elements are introduced into the device, the outputs of the 2nd and first - (p-1) -th channels of the multichannel parallel code converter in the pulse sequence are connected respectively о with direct inputs of the 2nd and the first - (p-1) -th and inverse inputs of the p'-and - (2p-1) -th elements And the second group, outputs (p + 1) -th - (2p-1 ) -th channels of a multi-channel parallel code converter in a pulse sequence are connected to the first inputs of the first (p-1) -th elements of the OR group, the second inputs of which are connected to the outputs of the same elements of the first group, the outputs of the first · - (p-1) - of the first OR element and the first OR element are connected respectively to the inverse inputs of the first - (p-1) -th and (2p) -th * and direct inputs of the (p + 1) -th (2p-1 ) of the th and rth elements of the second group, the outputs of i-ro and (p + i) -ro elements of the second group (i = 1, p-1) are connected respectively to the first and second counting inputs of the i-ro reversing drive , the installation inputs of which are the ith installation inputs of the device, the outputs of the rth and 2nd elements of the second group And are connected respectively to the first and second counting inputs of the pulse counter, the installation inputs and information output of which are respectively the rth installation inputs and device information output, second input and output the second element. And connected respectively to the output of the trigger and the second input of the second OR element.