SU1201847A1 - Unit-counting linearizing device with scaling - Google Patents

Abstract

NUMBER pulse linearizes DEVICE With scaling, comprising a controllable frequency divider, pulse-potential multiplier block memory address counter and the oscillator reference clock, and the information input apparatus connected to the clock input of the controllable frequency divider whose first output is connected to data pulse the input of the pulse-potential multiplier, the output of which is connected to the output of the device, the output of the reference pulse generator is connected to the control inputs of the controlled pulse A frequency solver, a pulse-potential multiplier and an address counter, the outputs of which are connected to the inputs of the lower bits of the address of the memory block, the inputs of the higher bits of the address of which are connected to the inputs of the scale factor of the device that are connected to the inputs of the setting of the division factor of the controlled frequency divider, the fact that, in order to increase the speed of the device, it contains a register, a pulse shaper and an OR element, and the outputs of the memory unit are connected to the information inputs of the register The SP outputs of which are connected to the potential information inputs of the pulse potential multiplier, the second output of the controlled frequency divider is connected to the first input of the OR element, the output of which is connected to the synchronization input of the register and the input of the pulse shaper, the output of which is connected to the counting input of the address counter, the second input element OR is connected to the output of the reference pulse generator.

Description

I 1

The invention relates to electron measurements and can be used to create multichannel information-measuring systems for measuring electrical and non-electrical quantities using nonlinear frequency frequencies of 6 volts.

J The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a structural cxeVa device; in fig. 2 is an embodiment of a pulse-potential multiplier.

The device (Fig. 1) contains a controlled frequency divider 1, a pulse-potential multiplier 2, consisting of a frequency divider 3 and an AND-OR 4 logic element, a memory block 5, a switch of 6 channels, an address counter 7, a generator 8 . pulses, register 9, pulse generator 10 and UTI element 11, the information input of controlled divider 1 being the device input, the output of divider 1 connected to the information input of divider 3, the output of which is connected to the first input of element 11, the second input of which is connected to the output of the generator 8 reference pulses and the installation inputs of the controlled divider, the counter 7 of the address and the divider 3, and the output from the control input of the memory register 9 and the start input of the pulse former 10, the output of which is connected to the information the input of the address counter 7, the inputs of the memory block 5 are connected to the outputs of the counter 7 of the address, to the control inputs of the divider 1 and to the outputs of the switch 6, the inputs of which are the manual and automatic settings for the channel number, the information inputs of the memory register 9 are connected to the outputs memory unit 5, and the outputs - with the second inputs of the AND-OR 4 element, the first moves of which are connected to the output of the divider 3, and the output of the AND-OR 4 element is the output of the device.

The variation of the approximation coefficient at the moment of termination of any section of the approximation is carried out by a fast overwriting of the memory stored in block 5 of the code memory into the register 9. The speed of execution of this onepaiTMH does not depend on the fast performance47

The VIE of memory block 5 (ROM) is determined by the speed of register 9, which is equal to the speed of the other nodes of the device. In this case, the storage in code 5 of the memory of the code corresponding to the next (i.e. transposing the data by one) number of the approximation segment is provided. The device is single-ended. The full cycle of its operation consists of the sum of two time intervals (formed at the output of the time generator t "at the initial installation of the main components of the device and

tp time. transform.

According to the previously known characteristics of the sensors and a given conversion error, the linearization device is calculated. He is reduced

to the determination of the number of approximation plots and the K approximation coefficients corresponding to each i-th plot 1. The coefficients K approximation are determined, in turn, by the number of the sensor (channel), therefore, the scale factor Kd, given by the controlled frequency divider 1, and the coefficient; multiply multiplier 2 corresponding to

this i-th approximation area. The values of the coefficients K are stored in memory block 5.

This breaks up the working range (for example, the numbers

 tnp) equal to the number of im-, pulses of the input frequency f, approximation areas. Thus, the length of the approximation region is determined by the serially connected controllable divider. 1 frequency and 3 frequency divider.

The device works as follows.

At the beginning of the next conversion cycle, a signal of a logical unit is formed at the output of block 8 of the reference time intervals, and during the time the initial setting of the controlled divider 1 is made,

divider 3 and counter 7 are in the state necessary for preparing the device for operation. For example, all of the listed nodes are set to the zero state, and the zero state

counter 7 corresponds to the first section of the approximation. Moreover, the duration of supplying the logical unit (tj, u) to the output of generator 8 determines the pause between adjacent time intervals t to convert the nonlinearized frequency f to numbers xA and is linearly related to the converted value X. The minimum duration is determined by the speed of the memory block 5, t. e. depends on the time t of sampling the specific type of used integrated circuit ROM. This is due to the fact that during time t, the code corresponding to the first section of the approximation must be set on the outputs of block 5.

At the moment of forming the differential 1/0 on the generator 8 code (i.e. at the time of the initial installation time t), the same differential 1/0 at the output of the OR II element is used to rewrite the code corresponding to the first section of the approximation from the outputs of block 5 to the register 9, as well as starting the former 10. The output of the former 10 forms a positive pulse, the duration of which can only be determined by the speed of the counter 7 of the address. A difference of 1/0 of this impulse transfers the counter 7 to the next (in this case, the state corresponding to the second section of the approximation).

The I / O difference generated at the output of generator 8 is simultaneously the beginning of the formation of the interval tnp during which the impulses of the input non-linearized and unscaled frequency f are converted into a pulse sequence f., At the output of the I-11PI element 4. More precisely, the number Mz. e „. is converted to M, d, linearly related to Noah, with the value X being converted.

A drop of 1/0 at the output of divider 3 signals the end of the next section of approximation. With the moment of occurrence of this difference at the output of the element OR at the beginning

5, an entry is made in the register 9 of the code corresponding to the coefficient of approximation of the next i-ro segment. Then I / O differential from the output of the rapper 10 counter 7

0 switches to a state one less than the number of this approximation area, i.e. in the (i + l) -ro state of the parcel.

Thus, the speed

5 of memory block 5 may be in Nn decreasing the speed of the remaining element base used to build the linearizing device. In this case, the number

the division ratio of the serially connected dividers 1 and 3, i.e. length of the plot of approximation, expressed in the number of pulses of the input frequency f.,.

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Claims (1)

NUMEROUS PULSE LINEARIZING DEVICE WITH SCALING, containing a controllable frequency divider, a pulse-potential multiplier, a memory block, an address counter and a reference pulse generator, the information input of the device being connected to the clock input of a controlled frequency divider, the first output of which is connected to the information pulse input potential multiplier, the output of which is connected to the output of the device, the output of the reference pulse generator is connected to the installation inputs of the controlled divider frequency, pulse-potential multiplier and address counter, the outputs of which are connected to the inputs of the least significant bits of the address of the memory block, the inputs of the highest bits of the address are connected to the inputs of the scale factor of the device, which are connected to the inputs of the division factor of the controlled frequency divider, characterized in that, with In order to improve the speed of the device, it contains a register, a pulse shaper and an OR element, _with the outputs of the memory block connected to the SS by the information inputs of the register, the outputs of which They are connected to the potential information inputs of the potential pulse multiplier, the second output of the controlled frequency divider is connected to the first input of the OR element, the output of which is connected to the synchronization input of the register and the input of the pulse shaper, the output of which is connected to the counting input of the address counter, the second input of the OR element is connected to the output of the generator “reference pulses. SU. „, 1201847>