SU1332519A1 - Digital nonrecursive filter - Google Patents

Abstract

This invention relates to digital technology. The purpose of the invention is to increase speed. The filter contains memory registers 1 and 11, multiplier 2, coefficient increment memory block 3, accumulator 4, adders 5 and 6, switches 7 and 8, shift registers 9 and 10, control unit 12, delay unit 13, and driver 14 pulses. The operation of the filter is carried out in cycles. At the same time, in the nth cycle, partial sums and an output count are calculated. The goal is achieved by calculating the new partial sums written to registers 9 and 10 in the order required for a given filter operation cycle. 2 Il. (L Wb / x.

Description

The invention relates to digital technology and can be used in digital signal processing systems.

The purpose of the invention is to increase the speed of the digital non-recursive filter.

Fig, 1 shows a block diagram of a digital non-recursive filter; 2 is a timing diagram of the control signals.

The digital non-recursive filter contains the first register 1 of memory, multiplier 2, block 3 of memory of coefficient increments, accumulating adder A, the first and second adders 5 and 6, the first and second switches 7 and 8, the first and second registers 9 and 10 of the shift, the second register of the P memory, control unit 12, delay element 13, driver 14 pulses.

The control unit 12 comprises a generator of 15 clock pulses, a counter 16, a decoder 17.

Digital non-recursive filter works in the following way.

The output sample Y (n) of the digital non-recursive filter is formed in accordance with the difference equation:

N-1

Y (n) and a.X (n-i),

where a. - weighting factors (counts of the impulse response); X (n-i) input counts.

The value of N in the digital non-recursive filter should be chosen odd, and the impulse response should be symmetric, i.e. but; Where

 i 0.1M-2; M (N + l) / 2. Then

each input sample X (p) multiplies two output samples Y (n + i) and Y (n + Nil) by the same coefficient a; while calculating Y (n + M-1) - by a factor a „.,.

Suppose, respectively.

The entire cycle of operation of the digital non-recursive filter (the cycle duration is equal to the sampling period) is divided into clock intervals. The first Bbrfi shift register 9 in this case has (N + 3) / 2 М + 1 4 cells, and the second shift register 10 has () / 2 2 cells. At the beginning of the zero clock interval, a pulse is fed to the control input of the first register 1 from the output of shaper 14, and the current count X (n) is written to this register, from the output of which it is fed to the second input of multiplier 2 during the whole cycle. To the first input of multiplier 2 from the output of block 3 in the zero cycle, the increment of the coefficient ya, a, a, in the first cycle i a, a, - a, and in the second cycle - la, a, comes. From the output of multiplier 2, the successively formed products ya.X (p), U a, - X (n), & but,,. X (n) is fed to the input of accumulating adder 4, which at the beginning of the cycle is set to the zero state by a pulse arriving at the reset input from the output of shaper 14. In the second half of each clock interval, the addition number of the next number arriving from the output of the multiplier 2, and the sum obtained in the previous tact. Thus, at the output of accumulating adder 4 in the second half of the zero cycle, the product (n) yoX (n) is formed, in the second half of the first cycle (n) (n) (n), and in the second half of the second cycle (n)) + a , X (n).

Coming from the output of the accumulating adder 4, the products of the current reference and coefficients are used to form in the nth cycle of partial sums of products $ "(n + |) a, X (p-3) + a, X (p-2) + (nl ) + + a, X (n), S (n + 2) (n-2) + + a, X (n-1) + (n),) a „X (n-1) + (n) and 5 "(n + 4) agX (n), related to the output samples Y (n + 1), Y (n + 2), Y (n + 3) and Y (ni-4), respectively, as well as to form output count Y (n).

Since the impulse response is symmetric, agX (n) is used when calculating simultaneously 5, (n) and S (n + 4), and, X (n) is used in the removal of Sjn + 1) and), and, X (n) - when calculating 5 (, (n + 2).

At the beginning of the zero cycle, the four cells of the first register 9 contain the partial sums obtained in the previous cycles, which are written in the following order: 5 „., (N + 1) (n-3) + a, X (n-2) (n- 1b

313

5 „., (P42) a X (n-2) -i a, X (n-l); S., (n + 3) a „X (p-1); 5„., (P) a „X (p-A) + a, X (n-3) - (n-2).

In the zero cycle, the control input of the first commutator 7 t of the first output of the decoder 17 receives the voltage of the logical unit, and the input of the first register 9 is connected through the first switch 7 to the output of the accumulating adder 4. The information is shifted in the first and second registers 9 and 10 at the end of each clock interval. At the same time, at the zero clock interval, the partial cell Sj, (n + 4) apX (n) from the output of accumulating adder 4 is recorded in the first cell of the first register 9, and (n) is output from the last cell. The remaining clocks at the control input of the first switch 7 contain a logical zero and the input of the first register 9 is connected via the first switch 7 to the output of the first adder 5. At the output of the first adder 5, the result of adding the numbers from the outputs of the accumulating adder 4 and the first register 9 is formed. When shifting in the first cycle, the first partial cell of the first register 9 records the new partial sum S (n + 3) Spo (n 3) + a, X (n), and in the second cycle - 5, (n + 2) S, (n + 2) + a, X (n).

Thus, by the time the n-th cycle ends, the partial sums 5 (n + 2), S (n + 3), 5 "(pM), 5"., (N + 1) are successively written in the cells of the first register 9.

At the same time, in the nth filter cycle, the partial sum Sp (n + l) and the output sample Y (n) S (n) are calculated using the second adder 6, the second switch 8 and the second register 10.

At the beginning of the zero clock interval in the second register 10 successively recorded S., (n + 1) avX (p – 3) + a, X (p – 2) + a X (n – 1), and Sn.i (n ) (p-4) + a, X (p-3) - + (p-2) a, X (p-1). During the zero and first clock cycles, the control input of the second switch 8 contains a voltage of logical, l, and the second register 10 is connected via the second switch B to the output of the second adder 6, which forms the sum of the numbers received

0 5 0

194

with the outputs of the accumulating adder 4 and the second register 10.

At the end of the zero clock when the information is shifted into the first cell of the second register 10, the full sum S (n) 5 ", (n) + agX (n) is recorded, and at the end of the first clock stroke the partial sum S (n + l) S, (n + l) -ia, X (n). In the last (second) clock cycle, the control inputs of the second switch 8 and second register 11 from the second output of the decoder 17 receive the voltage of a logical unit, the leading edge of which is overwritten by the calculated output sample Y (n) |, (n) from the last (second) the cells of the second register 10 are in the second register 11. The count Y (n) is stored in this register for the next cycle. In addition, at the last clock interval of the nth cycle, the second switch 8 switches, connects the input of the second register 10 to the output of the first adder 5, and when shifting to the first cell of the second register 10, writes a partial sum Sj, (n-H2) from the output of the first adder five,. and from the last cell, 0 S (n), by the end of the n-th

cycle in the cells of the second register 10 are sequentially written S (n + 2) and S (n + l).

Thus, at the beginning of (n + l) -ro

five

The cell cycle of both shift registers 9 and 10 contain new partial sums, written in the order required for the () -ro filter cycle.

The control unit 12 operates as follows.

. The frequency of the clock pulses (figa) at the output of the generator 15 in M times the sampling rate. The binary code from the output of counter 16, the conversion factor of which is equal to M, and the state changes on the leading edge of the clock pulse, arrives at the address input of unit 3. As a result, sequential sampling of the next increment of the coefficient at the beginning of each clock cycle is ensured.

At the same time, this code is fed to the input of the decoder 17, at the first output of which the voltage of the logical unit is present only in the zero cycle (Fig. 2a), and at the second output,

the course - in the last (M-1) th step

(figg). The former 14, on the leading edge of the voltage from the first output of the decoder 17, generates a pulse (FIG. 2d) for writing to the first register 1 and to zero the accumulator 4. The next sum in the accumulator 4 is recorded on the trailing edge of the clock pulse, and the shift in the first and second registers 9 and 10 on the trailing edge of the pulse, which is delayed relative to the clock in the element 13 for a time longer than the duration of the transition processes in the accumulating adder 4 | the first and second adders 5 and 6 and switches 7 and 8

(fig.2b).

Claims (1)

Invention Formula A digital non-recursive filter containing a multiplier, the first input of which is connected to the output of the memory unit, the increments of the coefficients, and the output is connected to the input of the accumulating adder, the first switch, the output of which is connected to the input of the first shift register, and the control unit, the first output of which is connected to input of the first switch, the second output is connected to the write input of the accumulating adder, and the third output is connected to the input of the memory unit of the increment coefficients, which differs Order 3848/55 Circulation 901 Subscription VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 five 0 five 0 five 96 In order to improve speed, the first memory register, whose input is the input of the digital non-recursive filter, the first adder, the second adder connected in series, the second switch, the second shift register and the second memory register, whose output is the output of the digital a non-recursive filter, a pulse shaper, and a delay element whose input is connected to the output of the control unit, and the output is connected to the combined control inputs of the first and second shift registers, the second input y the knife is connected to the output of the first memory register, the control input of which is combined with the reset input of the accumulating adder and connected to the output of the pulse former, the input of which is connected to the first output of the control unit, the output of the accumulating adder is connected to the combined first inputs of the first switch, the second adder and the first an adder whose output is connected to the second inputs of the first and second switches, the second inputs of the first and second adders are connected to the outputs of the first and second registers the shift, respectively, and the fourth output of the control unit is connected to the combined control inputs of the second switch and the second memory register.