SU1631558A1 - Special processor for digital filtration - Google Patents

Abstract

The invention relates to computing and is intended for use in digital signal processing systems. The purpose of the invention is to expand the functionality by performing recursive filtering. The goal is achieved due to the fact that the device includes a register 1, a multiplier 2, an accumulator adder 3, a memory block 4, a register 5, a counter 6, a register 7, a counter 8, a switch 9, a decoder 10, a block 11 constant memory and decoder 12 commands. 3 il.

Description

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The invention relates to computing and can be used in digital signal processing systems.

The aim of the invention is to enhance the functionality by performing recursive filtering.

Figure 1 shows a functional diagram of a specialized process; FIGS. 2 and 3 are time diagrams of its operation.

Specialized processor contains register 1, multiplier, accumulating adder 3, memory block 4, register 5, counter 6, register 7, counter 8, switch 9, decoder 10, block 11 constant memory (micro-instructions) and decoder 12 commands .

Specialized processor works as follows.

The first input of the processor receives digital samples of the input signal X (nT), and the second input - weights from the external ROM. The address bus of the external ROM is connected to the second output of the processor. The clock input frequency Tm is fed to the clock input. The conversion factors for counters b and 8 are the same and equal to N. The first output of a specialized processor receives digital samples of the output signal Y (nT). The mode of operation of the device is determined by the logic levels at the control inputs of the device.

The amplitude-frequency characteristic of the filter, built on the basis of a specialized process, is determined by the values of the weighting coefficients.

Consider the operation of a specialized processor in the mode of a recursive digital filter consisting of cascaded and connected second-order recursive links. At the same time, the number of links is L N / a, where a is the number of periods of the clock frequency required to process one link. In this mode, the state of the control inputs is as follows: C1 1; C2 1; NW 1.

At the output of the switch 9, a counter 6 is connected in such a way that all bits of the counter 6, except the first and third, are connected to the address input of the block 4. This ensures the repetition of the cells of the memory block 4 during the calculation process.

The value of the output sample Y (nT) is calculated by the formulas:

V (nT) M - X (pT) + A1 V ((n-1) T) +

+ A2-V ((n-2) T); (1)

Y (nT) - BO -V (nT) + B1 V ((n-1) T) + -

+ B2 -V ((n-2) T), (2)

where n is the number of input reference;

X (pt) - the value of the input sample;

V (nT (, V ((n-1) T), V ((n-2) T)) is the output value of the recursive part of the link in the present and the two previous cycles of calculations;

VO, B1, B2, A1, A2 - weights of the filter;

M - scaling factor.

The maximum transfer coefficient of the recursive part of the Kmax link is 1, therefore, the scaling coefficient M is provided at the filter input, the value of which is selected from the condition M 1 / Kmax.

The coefficients A1 and B1 can take values from 2 to -2, therefore, in order to avoid overflow in the multiplier, one should use half values of the coefficients, the values of which by modulus do not exceed one.

With this in mind, in formula (1), instead of A1 V ((n-1) T), you should write 0.5 A1 -V ((n-1) T) + 0.5-1 A1 -V ((n-1) T) Similar changes in formula (2).

At the zero step, i.e. when the counter is in the zero state 6, register 1 is in the Storage mode, memory block 4 is in the Read mode, register 7 is in the Storage mode, register 5 is in the Read mode.

The inputs of the multiplier 2 are supplied with factors V ((n-1) T) from block 4 and 0.5-1 from the external ROM. The accumulating adder 3 records the result of the previous multiplication.

By the next pulse fr, the contents of counter 6 are incremented by one. From accumulator 3, register 5 records the result of the calculations Y ((n-1) T) of the previous cycle. By a pulse from the output of block 11, the accumulating adder 3 is zeroed and the product 0.5-A1 V ((n-1) T) is written into it. The multipliers V ((n-1) T) from block 4 and 0.5-1 from the external ROM are input to the multiplier.

In the second step, the result of the multiplication is written to the accumulating adder 3, the factors V ((n-2) T) from block 4 and the coefficient A2 from the external ROM enter the multiplier 2. Register 1 is written to the input count X (pT) in step N-1.

In the third step, block 4 switches to the Storage mode, and the accumulator V ((n-2) T) -A2 is written to the accumulating adder 3. The inputs of the multiplier are input count X (pT) from the output of register 1 and the scaling factor M from the external ROM.

In the fourth step, register 1 switches to storage mode. The inputs of the multiplier 2 receive the factors V ((n-1) T) from block 4 and 0.5-81 from the external ROM. AT

the accumulating adder 3 is recorded as the product X (pT) -M.

In the fifth step from accumulating adder 3, the output count of the recursive part of link V (nT) is recorded in register 7. The inputs of the multiplier 2 receive the factors V ((n-1) T) from block 4 and 0.5-B1 from the external ROM. The accumulating adder 3 is zeroed and the product V ((n-1) T) -0.5; IN 1.

At the sixth step, the product V ((n-1) T) -0.5 B1 is written to the accumulating adder 3, and the factors V ((n-2) T) from block 4 and the coefficient B2 from the external ROM are input to the multiplier.

In the seventh step, the memory block 4 switches to the Record mode and, at the address where the count V ((n-2) T) was located, is recorded from register 7 the count value V (nT), which is simultaneously fed to one input of the multiplier 2, while the input of the multiplier 2 from the external ROM is the VO coefficient. In accumulating adder 3. is written e V ((n-2) T) -B2.

In the eighth step, the calculation of the input sample Y (nT) of the first link is completed, which is written to register 7. The value of Y (nT) is the input sample for the second link. The accumulator sum 3 is zeroed and the product V ((n-1) T) -0.5 -A1 is written into it. The inputs of the multiplier 2 receive the factors V ((n-1) T) from block 4 and 0.5-1 from the external ROM.

The calculation process is then repeated. The output count of the next link is the input for the next one.

Thus, eight periods of frequency fr are spent on calculating the output sample, hence the number of links L N / 8.

The output sample Y (nT) of the recursive filter is written to the second register 5 in the first step of the second computation cycle. After each calculation cycle, the second bit of the address of block 4 is inverted in switch 9, i.e. the high and low delay elements are swapped, which is equivalent to shifting the samples in the delay elements.

When the value of the control inputs C1 O, C2 1, C3 1, the decoder 12 commands generates control signals, under the influence of which the encoder 10 together with block 11 additionally generates the recording signals at (N / 2-1) step and reading at (N / 2 + 3) step for register 1; at (N / 2 + 1) step, a write signal for register 5. In addition, register 7 switches to

Storage at (N / 2 + 3) step to exclude the transfer of the output sample of the first filter to the input of the second.

In this way, two recursive digital filters (RCFs) of N / 16 second-order recursive links are implemented.

When the value of the control inputs C1 O, C2 0, NW 1, the decoder 12 commands generates the control signals, under the influence of which the decoder 10 together with block 11 additionally generates the write signals to (N / 4-1), (N / 2-1) and (3N / 4-1) steps and read in (N / 4 + 3), (N / 2 + 3) and (3N / 4 + 3) steps for register 1, Ha (N / 4 + 1), ( N / 2 + 1), (3N / 4 + 1) steps — the write signal for register 5. In addition, register 7 switches to Storage mode at (N / 4 + 3), (N / 2 + 3) and (3N /4-.3) steps to exclude the transfer of the output sample of one filter to the input of another. This is how four RCFs of N / 32 links are implemented.

Consider the work of a specialized processor in the non-recursive digital filter mode. The order of the filter is determined by the conversion factor of the counters b and 8 and is equal to T 1. The control inputs for the operation mode in this c are connected to a zero potential, i.e. C 1 C 2 C 0.

The output sample Y (nT of non-recursive digital filure is determined by the formula

Y (nT) S1X ((n-l) T) -B, (3)

I o

The first input of the device receives samples of the input signal X (pT), and the second input contains the filter coefficients from an external ROM, whose address input is connected to the second output of a specialized processor. The clock input with the frequency rm comes to the clock input, and the output samples of the output Y (nT) are output.

The output of the switch 9 switches the output of the counter 8, which determines the address of the block 4. The counting input of the counter 8 receives the clock pulses from the output of the block 11, Register 7 does not participate in the operation and is switched to the Storage mode. At the zero step, when the counters 6 and 8 are in the zero state, from the external ROM one input of the multiplier 2 receives the VO coefficient, to the other input from the output of the register 1 - the input signal X (pT) recorded on the previous step. At the same time, unit 4 switches to the Record mode and at the zero address the sample X (pT) of the input signal is recorded. The accumulating adder 3 records the product X ((p-1) T) -BO.

By the next pulse fr, the contents of counters 6 and 8 are incremented by one, Register 1 switches to the Storage mode, block 4 to the Reading mode. From accumulating adder 3 to register 5, the result of the previous cycle of computing the output sample Y ((n-1) T) is written, accumulating adder 3 is nulled, and the product X (pT) -BO is written to it, the multipliers X ((n -1) T) from block 4 and B1 of the external ROM.

In the second step in. the accumulating adder 3 is recorded as the product X ((p-1) T) B1. The inputs of multiplier 2 receive factors X ((p-2) T) from block 4 and B2 from the external ROM.

This continues up to the (N-1) step. In this case, counters 6 and 8 are in the (N-1) state. The inputs of the multiplier 2 receive factors X ((n-N-1) T) from block 4 and B (N-1) from the external ROM. The accumulating adder 3 records the product X ((n-N-2) T) - B (N-2). Register 1 is written counting X ((n + 1) T) of the input signal.

By the next pulse fr, the counter 6 switches to the zero state, and this pulse does not arrive at the counting input of the counter 8 and its contents do not change. Block 4 switches to Record mode. From register 1, the count X ((l + 1) T) is fed to one input of multiplier 2 and simultaneously recorded in block 4 at address (N-1), i.e. in the cell where the X count was ((n-N-1) T). On the other input of the multiplier the coefficient VO comes from the external ROM.

The accumulating adder 3 records the product X ((n-N-1) T) B (N-1).

By the next pulse fr, the contents of counters 6 and 8 are incremented by one. The inputs of the multiplier 2 receive factors X (pT) from block 4 and the coefficient B1 from the external ROM. From the accumulating adder 3, the output count Y (nT) is written to register 5, the accumulating adder is zeroed and the product X ((n + 1) T) -BO is written to it.

Then the cycle repeats.

Thus, the shift of counts in the cells of the memory block 4 is performed by shifting the cells of block 4 relative to the addresses of the ROM cells.

When the value of the control signals C1 O, C2 1, NW 0, the decoder 12 command acts on the control inputs of the switch 9 and the decoder 10. At the same time, all bits of the second counter 8, except the oldest one, are connected to the output of the switch 9. The highest bit of switch output 9

the higher bit of counter 6 is connected. This is necessary to divide the cell area of block 4 into two parts: for the first and second filters respectively. Good dock

5 filter in this case is equal to (N / 2-1). The decoder 10 together with block 11 additionally generates the following signals Writing into register 1 in (N / 2) step, Zeroing accumulating adder 3

10 at (N / 2 + 1) step, Writing to register 5 at (N / 2 + 1) step. Thus, two non-recursive filters of the order (N / 2-1) are implemented. When the value of the control signals is C1 1, C2 1, NW 0, the decoder 12

15 commands affect the control inputs of the switch 9 and the decoder 10. At the same time, all the bits of the counter 8 are connected to the output of the switch 9, except for the two high bits (the last and the last but one). The senior (last and last) bits of the counter 6 are connected to the two older 20 bits (the last and the last) of the output of the switch 9. This ensures the division of the cell area of the block 4 into four parts 25 for the first, second, third and fourth filters, respectively. The filter order in this case is (N-1). The decoder 10 additionally generates the following signals: Record for the register 1 Ha (N / 4-1)

30 and (3N / 4-1) steps, Reading for register 1 at (N / 4) and (3N / 4) steps, Zeroing accumulating adder 3 at (N / 4 + 1) and (3N / 4 + 1) steps.

In this way, four non-recursive filters of the order (N / 4-1) are implemented.

Claims (1)

Invention Formula Specialized processor for 40 digital filtering containing the first and second registers, the first counter, the memory block, the multiplier and accumulating adder, the output of the first register connected to the information input-output 45 of the memory unit and the first information input of the multiplier, the output of which is connected to the information input of the accumulating adder, the output of which is connected to the information input of the second register 50, the output of which is the information output of the processor, the information input of which is the information input of the first register, the second information input multiplier 55 is the input of the setting of the coefficients of the processor, the clock input of which is interconnected counting input of the first counter and the synchronization inputs of the multiplier and accumulating adder, characterized in that extending the functionality by performing recursive filtering, a third register, a second counter, a command decoder, a switch, a decoder, and a microcommand constant memory block are entered, the first to ninth outputs of which are connected respectively to the second input of the second register, the zero accumulator input the adder, the control inputs for writing and reading the memory block, the enable inputs for receiving and issuing the first and second registers and the counting input for the second counter, the KOTOpdro information output is connected to ervomu data input switch, whose output is connected to the address input of the memory data output per0 The first counter is connected to the second information input of the switch and the first input of the decoder, the output of which is connected to the address input of the microcommand memory block, the read control input of which is connected to the processor clock input, the input for selecting the mode of the command decoder, the first and second outputs which are connected respectively to the control input of the switch and the second input of the decoder, the output of the accumulating adder is connected to the information input of the third register, the output of which connected to the first information input of the multiplier and information input-output of the memory block. Outputs 5lok And / g 1gggii1llllllllllllplpl / 7 gshlgiishshgl dllp plgshl lf o.1  1234587 8 9 WIHinWS TJ g  3 rm and and and allplice plpl tllj1shsh in FIG. 2 WIHinWS P LT - b / current 11 Inputs block 11 , / g 1JTJTJTJTJT-TLTI / g JIJOJIJOTIJIJIJ7 S ri JTJTJnjnj-U l 9 Fig.Z Inputs block 11