SU904201A1 - Digital filter - Google Patents

Description

(54) DIGITAL FILTER

Claims (2)

The invention relates to electrical measuring and computing techniques and can be used in digital signal processing systems. A device for performing digital filtering is known, containing two cyclic memories, multipliers and adders, filtering the signal using the convolution formula, but calculating the noise of the pairs of numbers h; and Hz-1 is performed on one or a small number of til multipliers. In this digital filtering device, hardware costs are significantly reduced, but it takes longer to calculate one of the convolution counts, since arithmetic operations are performed sequentially on the same equipment. The closest technical solution to the proposed is mouth-. A digital filtering device containing a block of coefficients of the impulse response coefficient Bd, the first input of which is the input for writing an array of numbers bi, the second input and output are connected to the first address counter and the input of the first register respectively, the output of which is connected to the first input of the multiplication device connected its output to the input of the accumulating adder, the output of which is connected to the cyan-and-anap converter, the second input of the multiplication device is connected to the output of the adder, the first and second inputs of which It is connected to the outputs of the second and third registers, respectively, the first and second memory blocks of input samples, the first inputs connected to the second and third address counters, respectively, the second inputs connected to the outputs of the fourth and fifth registers, the output of the third register is connected to the input of the fifth register and the first input of the fourth register, the second input of which is connected to the output of the first memory block of the input samples, the first input of the third register is the input of the filter, and the second input of the third register in od .vtorogo register connected to the outputs of the first and second memory input samples respectively 2 blocks. The disadvantage of the device is the low speed associated with non & time consuming to perform the shift operation of the input array and with a large number of multiplication operations. A large number of multiplications leads to a sharp decrease in the speed of the device, and the time spent increases linearly with the order of the filter N. The increase is fast. The goal is achieved by the fact that in a digital filter containing an input sample memory block, the first register is a pulse shaper, whose output is connected to the input of the first address counter, the output of which is connected to the first input of the coefficient memory block, the output of which is connected to the input. register, the output of which is connected to the first input of the multiplier, the output of which is connected to the input of the first accumulating adder, the output of which is connected to the input of the digital-to-analog converter, the output of which is analog filter output and output. The first accumulating adder is a digital output of the filter, the output of the memory block of the input samples is connected to the input of the first register, the first input of the memory block of the input samples is the input of the filter, and the second input of the memory block of coefficients is the input of the coefficients, the second and the third address counters, block ranks, descrambler, adder, multiplexer, second accumulating adder and synchronization unit, the first output of which is connected to the input of the second address counter, the output of which is En with the first input of the rank memory block, the first code of which is connected to the first input of the adder and the input of the decoder, the output of which is connected to the second input of the memory block of the input samples and the second input of the multiplexer, the output of which is connected to the first input of the second accumulating adder, the output of which connected to the second input of the multiplier; the second input of the second accumulating adder is connected to the output of the pulse former, the input of which is connected to the second output of the rank memory block, the second input of which is the input The second entry of the synchronization block is connected to the input of the third address counter, the output of which is connected to the second input of the adder, the output of which is connected to the third input of the memory block of the input samples, the first input of which is combined with the second input of the multiplexer, the third input of which is connected to exit first register. A digital filter circuit is illustrated in the drawing. The filter contains input 1 of the recording of the coefficients of the impulse response, driver 2 pulses, address counter 3, block 4 of the coefficient memory, register 5, multiplier 6, accumulating adder 7, digital-to-analogue converter 8, analog 9 and digital 1О, outputs, accumulating adder And, decoder 12, the input 13 of the record of ranks of i factors, the block of memory of ranks 14, the adder 15, the block of memory of 16 input samples (by address input), the register 17 and multiplexer 18, the address counters 19 and 20, the input of the filter 21, the block 22 of synchronization. The digital filter works as follows. Before starting the signal processing by. Input 1 in block 4 of the coefficient memory records an array of various filter coefficients, and block 14 of the rank memory at input 13 records an array of numbers representing the numbers of coefficients of the impulse response (FIR) arranged in a sequential order. The number of the address of the cell of the rank memory block to which the coefficient hti is written and is the rank j of this coefficient. Thus, each coefficient h is matched; some integer j, which is the cell address of the rank memory block, into which the number M is written. First; The ranks of the FIR numbers, whose numerical values are equal to b, are recorded in the ranks memory block. The number h itself is written into the first cell of memory block 4, The memory cells K through K-ifl i of block 14 are recorded from the FIR number, the numerical values of which are hj, and the number h itself is written into the second cell of block 4 pa KI m ti, etc. The cells of the memory block 14, where h l, 2, ... i (and - l), write the FIR numbers, the numerical values of which are written in the (+ 1) th cell of the memory block 4 and are equal. The current sampling of the input signal X is fed to the input 21 and then to the information input of the memory block 16 and the input of the multiplexer 18. In the initial state, the accumulating adders 7 and 11, the counters 2 and 19 are in the zero state. In the address counter 2O, having a recalculation module equal to N-1, some code a is recorded in the initial state. After the input signal X (p) arrives at the input 21 of the next counter, the calculation of the reference and / and convolution is performed as follows. Block 22 generates N pulses that are fed to the input of address counter 19. In this case, from block 14, memory is successively read to the input of adder 15, the number of coefficients of the impulse response of the filter W, the sum of which with the number a is the address of the memory cell of block 1 of which readout of the input signal X (output through register 17 and multiplexer 18 to the input of accumulating adder 11. First, from the cells with addresses, successively read from the number N of coefficients of impulses their characteristics numerically equal to h cells with addresses of memory block-1 are sequentially read samples X (. and-1) through register 17 and multiplexer 18 to the input of accumulating adder 11. After reading the number of the filter coefficient from the cells with address .. and;, - in accumulating adder 11 the sum of k samples of the input signal Tx is stored (Simultaneously with the formation of this sum, we accumulate accumulator 11 from memory block 4 into register 5 to read the value of the code b | . Cell addresses of the memory block 4 are formed by an address counter 3 having a conversion module equal to I. The sum accumulated in adder 11 is multiplied in multiplier 6 by a factor h and written to accumulating mat 7. When reading the FIR number from the cell with address j 1, memory block 14 produces a signal that triggers the driver 2 pulses, at the output which is delayed for 1b of calculating the product h, 4. PD, a pulse is formed, which flushes the accumulating adder 11 and changes to the state of the address counter 3. In time this pulse is located between and, the pulses generated by block 22. The next group from Kj. impulses generated by block 22, in a similar way, forms the sum h-, which is added to the previously calculated sum in accumulative adder 7. Thus, after the impulse n-i, formed by block 22, the sum G is recorded in accumulator 7 calculating the amounts from a certain cell of the rank memory block 14, the code corresponding to the number of the impulse response coefficient factor 1 O, which can be interpreted 45) is read out by the decoder 12, then by the output signal from the decoder 12 the memory block 16 of the input samples eklyuchaets input sample in the recording mode X (s) in the cell with the address, and the output multiplexer 18 is transmitted ora input signal sample. . V After the formation of all N-1 pulses has been completed by block 22, output 10 of accumulating adder 7 is sampled output signal ij 1) in digital form, and output 9 of the D / A converter takes the current value of the analog output signal. The computation of the convolution reference is completed by the formation of the second output by the impulse unit 22, which changes the address counter 20 by one. In time, this form impulse is fueled after the F-1 impulse with a delay necessary to complete the calculation of the reference | (and). Thus, by the time of the next sample of the input signal x (and-i), the number cifl is written in the address counter 20. This provides an automatic shift of the array of input samples by one, which is necessary for the next sample u (and + -1) of the output signal 90. The shift of the array of input samples is performed as follows. Let at the cth time of the sampling of the input signal be recorded in the memory block 16 as follows: sample x (i-lh-1) into the cell with address C sample) f (and -f / - -) into the cell with address ((Q -ll)) M-1, and the samples (and-i) are written in a cell ((ot-H M -1-4,)) M-,), where, 2M-l. In block 14 of the rank memory and block 4 of the coefficient of information of the record / on are as follows. The cell of the memory block 4 with the zero address records the | C code of the coefficient sj,; ,, and the cell O of the memory 14 with the zero address records the O code. The following cells of the memory 14 record the numbers of the FIR filter whose numerical values are The number recorded in memory block 14 corresponds to the corrected sequence of coefficients, i.e. if the coefficient is then in block 14 of memory, record hfi, - -, i- “; The number N corresponding to this coefficient is shown. The location of the coefficients within the group and; the arrangement of the very groups of coefficients can be arbitrary, the assignment of a zero rank to the hw- / i coefficient is essential. With such an organization of the filling of the memory block 4 and the memory block 14, the calculation of the counting of the output signal ij (and) is given as follows. First, from the memory block 14, the code O is read at the zero address, and at address 4-O from the memory block 16, the sample x (HNil) is read, and the product AND-N + I is calculated. Then, the next cell of the memory block 14 reads the code corresponds to the coefficient A, and from the cell of the memory block 16 with the address ((a + Nf-i)) (l reads the sample X (and -1) JTO corresponds to the calculation of the product Y and-ti, etc. If from some cell of memory block 14, an Ml code was read which corresponds to the coefficient, bj, then, by a signal from decipher 12, the input sample X is written to the cell of the memory block 16 with the address equal to A. ЧТ9 1 ФНВОДИТ to update the information in the memory block 16. When calculating the count y (and + 1), the initial state of the counter 20 is 18 Of 1. Thus, when you first access the cell of the block 14, a code is formed at the output of the adder 15 (X + 1, and a chi-N + i sample is read from memory block 16, which corresponds to the calculation of C) using the non-recursive filtering formula with and -ti. The current value of the input sample is recorded in the cell with the address from (. + 1. Changing the initial state of the counter 2O by one, the array of input samples is updated and shifted by one. The proposed device favorably differs from the known one. The calculation time of the convolution count is t .tyn - N4 - CsCs Since multiplication is a device operation speed determining operation and H1 "(d-vl) for large N, the device speed is higher. In addition, the memory block is not required to overwrite the array of input samples, h then, in parallel operation of two memory blocks of input samples, it will be possible to obtain a gain in computation time equal to 0. Formula of the Invention A digital filter containing an input sample memory block, the first register, pulse generator, the output of which is connected to the input of the first address counter, the output of which is connected to the first input of the memory of coefficients, the output of which is connected to the input of the second register, the output of which is connected to the first input of the multiplier, the output of which is connected to the input of the first accumulator The mapper, whose output is connected to the input of a D / A converter, the output of which is., is the analog output of the filter, and the output of the first accumulating adder is a digital output of the filter, the output of the memory block of the input samples is connected to the input of the first register, the first input of the memory block of the input the samples is the input of the filter, and the second input of the coefficient memory is the input for recording the coefficients, characterized in that, in order to improve speed, the second and third address counters are entered into it iks, rank memory block, decoder, adder, multiplexer, second accumulating adder and synchronization unit, the first output of which is connected to the input of the second.address counter, the output of which is connected to the first input of the memory block of the first and ranks, the first output of which is connected to the first input the adder and the input of the delimiter, the output of which is connected to the second input of the memory block of the input samples and the second input of the multiplexer, the output of which is connected to the first input of the accumulating adder, the output of which is connected to the second input intelligently The second input of the second accumulating adder is connected to the output of the pulse body, whose input is connected to the second output of the rank memory block whose second input is the filter write entry input, the synchronization block input is connected to the third counter of the address counter, the output of which is connected to the adder input The output of which is connected to the third input of the memory block of the input samples, the first input of which is combined with the second input of the multiplexer, the third input. which is connected to the output of the first register. Sources of information taken into account in the examination 1. Gold B., Rabiner L. Theory and digital signaling. M., Mir, 1978. 2. USSR author's certificate number 636616, cl. Q About F 15/36, 1876 (photon).