SU1185351A1 - Device for processing images - Google Patents

Abstract

1. DEVICE FOR PROCESSING IMAGES, containing a shift unit, the control input of which is connected to the first output of the synchronization unit, the second output of which is connected to the information input of the shift unit and the address input of the first memory unit, the output of which is the information output of the device, different that, in order to increase the operation, a constant memory block, a multiplier, an adder and a second memory block are inputted into it, the output of which is connected to the first input of the multiplier, the output of which is connected to the first one the input of the adder, the output of which is connected to the information input of the first memory block, the output of which is connected to the second input of the adder, the third output of the synchronization block is connected to the address input of the permanent memory block, the output of which is connected to the second input of the multiplier, the information output of the shift block is connected to the address input of the second memory unit, the information input of which is the information input of the device. 2. The device according to claim 1, from which the synchronization unit contains an adder, a decoder, four counters and a generator (L clock pulses, the output of which is connected to the counting input of the first counter, the transfer output of which is connected to the counting inputs of the second and The third counters, whose information outputs are connected respectively to the input of the decoder and the first input of the adder, the second input is connected to the information output of the fourth counter, the counting connector of which is connected to the installation input tego counter and connected to an output of the decoder, the adder output data outputs of the first and second counters are respectively first, second and third outputs sync block.

Description

eleven

The invention relates to automation and computing and can be used in information processing systems, information and measurement systems.

The purpose of the invention is to increase speed.

FIG. 1 is a block diagram of an image processing device; in fig. 2 — specific implementation of the arithmetic unit; in FIG. 3 a synchronization unit.

The image processing apparatus comprises a synchronization unit 1 ,. memory block 2, persistent memory (coefficients) 3, arithmetic unit 4, memory block 5, shift unit 6.

The type of processing determines the set of operations performed by the arithmetic unit 4. FIG. 2 shows the implementation of the arithmetic unit for performing two-dimensional cyclic convolution.

;, M-V-1

f L. - 51 h. . g

k.e

  ij 1 I --J 3

where f „- counts processed

(output image);

  , g L

i4e.

cr k O, K, G Oh, L - 1,

L is the number of samples per line

images;

K is the number of samples in the image column;

h.- coefficients of the weight function with which cyclic convolution is performed;

e k, e samples of the input image The arithmetic unit contains the series-connected multiplier 7 and adder 8.

The synchronization unit, shown in Fig. 3, contains successively connected clock generator 9, sample address counter 10, coefficient address counter 11, and a shift generation circuit 12, which in turn contains an adder 13, a vertical shift counter 14, a horizontal shift counter 15 and a decoder 16 defining the moment when the addresses of the coefficients are q. N + 1, q, 0, (M-1).

The device begins to function when on the information input

512

block 5 will start c) scrolling through the samples of the input and image, at this moment the shift made by the shift block 6 is zero, the contents of the memory block 2 is also zero, the counts are recorded in successive cells of the block 5 and simultaneously pass t to the output of block 5 and arrive at the input of the arithmetic unit 4, to another input of which is from the memory block

3turns the coefficient hj, f

In the arithmetic unit 4 there are counts g,. g multiplied by a factor

The TM-I, N-1 multiplier and through the adder are fed to the input of the memory block 2. The products g j, h d, |, are recorded from the starting address into successively located

cells of memory block 2. The addresses that are written in memory block 2 in this cycle coincide at each time with the addresses at which readings g Kg from memory block 5 are read. The first cycle ends when in memory block All 5, all KL samples of the input image will be recorded and in memory 2 will also be recorded.

KL products g.g h m-, k-y

k (0, b-1), t 0, L-1. In the next cycle, block 1 in shift block 6 is assigned a shift equal to one, i.e. the addresses at which samples will be sampled from memory block 5 are at one time more than the addresses that are read and written to memory 2. At the same time, from block i, a signal is sent to the input of the coefficient memory block 3, changing the address at which the coefficient is sampled. From the coefficient memory block 3 will be selected

coefficient bdd., .2 which goes to the input of the arithmetic unit 4. To the input of the arithmetic unit

4 access t - counts, and to another input of the arithmetic unit 4 the product g k, p h d ,. . ,

The samples g (c, eti in the multiplier of the arithmetic unit 4 are multiplied by the coefficient b ,,, n-t. The resulting products are added to

the adder of the arithmetic unit 4 with the products g c h,., -) coming from the memory block 2. The resulting partial sums, x m 1, N-1 8k, e 1., bd,., J are written in block 2 on places of works g „.fh d ,, j. The second cycle ends when the entire contents of memory block 5 is read again, and in all the cells of memory block 2 the sums of the form will be formed: (8k, 8 h "., C, + g, e ,,. H.,) , K-1, t O, L, -1. B. the next cycle from the memory block, ti coefficients 3, the coefficient bd ,, | and the shift in the shift block 6 will be set to 2, and the cycle is repeated. As a result of this cycle, the sums M-l, j will be formed in the memory block 2 after the N repetitions of such cycles, the sums will be accumulated in the memory block 2:

N-

Zis

K.EH - j -1

J - 0

Further, the previously mentioned N cycles are repeated for the coefficients M-2, j J 0 N-1 and the magnitudes of the shifts L + J, j O, N-1, as a result of which 1185 10 5 2Q 25

The output samples fx4MMetN-l are successively received from memory 2 to the output of the device, and memory 2 is zeroed out. 514 of their execution in the block of tags 2 will accumulate the sum of the following N cycles from the memory block of coefficients 3, the coefficients h .., j 0, N-1 will be selected and in the block of shifts 6 the values of shifts will be set equal to 2L + J J O, N-1. As a result, sums m − 1 M − 1 .P N-j- -J will be accumulated in memory block 2. After M N N cycles, sums of the following form will be formed in memory block 2:. ,,,., p, .j .; h .. which are output samples of the processed image

Rig. 2

Claims (2)

1. DEVICE FOR PROCESSING IMAGES, containing a shift unit, the control input of which is connected to the first output of the synchronization unit, the second output of which is connected to the information input of the shift unit and the address input of the first memory unit, the output of which is the information output of the device, characterized in that, with In order to increase performance, a permanent memory block, a multiplier, an adder and a second memory block are introduced into it, the output of which is connected to the first input of the multiplier, the output of which is connected to X to the first input with a matrator, the output of which is connected to the information input of the first memory block, the output of which is connected to the second input of the adder, the third output of the synchronization block is connected to the address input of the permanent memory block, the output of which is connected to the second input of the multiplier, the information output of the shift block is connected to the address input of the second a memory unit, the information input of which is the information input of the device. 2. The device according to claim 1, characterized in that the synchronization unit comprises an adder, a descrambler Q, four counters and a clock pulse generator, the output of which is connected to the counting input of the first counter, the transfer output of which is connected to the counting inputs of the second and third counters, the information outputs of which are connected respectively to the input of the decoder and the first input of the adder, the second input of which is connected to the information output of the fourth counter, the counting input of which is connected to the installation input of the third counter and Connected to the decoder output, the adder output, the information outputs of the first and second counters are the first, second, and third outputs of the synchronization block, respectively. 1 185 351 i