SU1137583A1 - Corrector - Google Patents

Abstract

CORRECTOR containing shift register

Description

The invention relates to telecommunication engineering, in particular to transmitted (; s, and is intended to increase the noise immunity of reception by reducing the effect of intersymbol distortions arising due to frequent distortions in the transmission path. A corrector is known that has an analog line delays by N + M cycles, the input and taps of which are connected to the subtracting inputs of the adder through adjustable attenuators, the N-and the removal via a constant resistor connected to the summing input of the above-mentioned adder, the output of which is connected in parallel to the summing input of the correction error determinant, to the input of the filling sign shaper and to the input of the regenerator of the filling, the output of which is connected to the subtractive input of the aforementioned correction error determinant. The device also contains N + M formers of the intersymmetric free-form interference (SMP) each I8 of which includes a modulo-two modularly connected in series, one of the inputs of which is connected to the output of the delay register for N cycles, to the input of which the correction error is output from the output correction error bodies, averaging reversible counter, battery (accumulating reversible counter, digital-analog converter) and the above-mentioned adjustable attenuator, another modulo-two input and another input of the adjustable attenuator of the first SMP driver are connected respectively to the shift register input with a common lead on the V + M cycles, to the input of which the parcel sign is output from the exit. The other input of the modulo two adder and the other input of the adjustable attenuator of the second SMP driver are connected respectively to the output of the first shift register cell and to the first tap of the delay line, etc. to the N-th withdrawal of the delay line and, to the N-th output of the N -th cell of the shift register and for which the form of the United States school is not provided, each input of the modulo two adder and another input of the regulator attribute83 of the Nyuator (M + 1) -th the driver is connected respectively to the output (M + 1) of the shift register cell and to (W -fO-My tap of the delay line, etc. to the other input of the modulo two and the other input of the last attenuator (K) + M) of the first SMP generator, connected respectively to the output (H + M) of the th shift register cell and to (N + M) th to the wire (output) of the delay line L. However, this device does not provide the required accuracy of correction and is quite difficult. The closest to the proposed technical essence and the achieved result is a corrector containing a register shift, shapers, intersymbol interference component, each of which consists of serially connected modulo two, element I, the second input of which is the input of clock pulses reversible counter, increment decoder, accumulator and multiplier, and in series: a diffraction delay line, the input of which is connected to the shift register input through The secondary circuit, the adder, the memory strobe element and the amplitude discriminator, the input and output of which are connected respectively to the inputs of the correction error determinant, the output of which is connected to the first inputs of modulo adders two, the second inputs of which are connected respectively to the shift register outputs and to the second inputs of the corresponding the transponders, the terminals are connected to the subtraction inputs of the adder I. However, the known device does not provide high accuracy of correction. The circuit of the invention is an increase in the accuracy of correction. The goal is achieved by the fact that, in the offset containing the shift register, the drivers of intersymbol interference, each of which consists of a serially connected modulo-two adder, an And element, the second input of which is the input of clock pulses, a reversible counter, a decoder increment 3

Research institute, accumulator and multiplier,

and a serially connected digital delay line, whose input is connected to the shift register input via a threshold circuit, an adder strobe memorization element and an amplitude discriminator, the input and output of which are connected respectively to the inputs of the correction error determinant whose output is connected to the first inputs of modulator two modulators , the second inputs are connected respectively to the outputs of the shift register and the second 4 inputs of the corresponding multipliers, the outputs of which are connected to the subtraction codes with Odmator, an OR element is introduced, and the output of each increment decoder is connected to the corresponding input of the OR element, the output of which is connected to the second inputs of reversible counters.

The drawing shows a structural electrical corrector circuit. The corrector contains a superfluous 1 delay with a total delay of N ticks, an adder 2, a strobe transform element 3 with memory, akg1litud1 discriminator 4, a correction error identifier 5, shifting the register b with a total delay of N + M cycles, forwarders 7: (M each of which consists of: serially connected JTopa 8 modulo two, element I 9 of a reversible counter 10, decoder 11 increments combined with a smart one per correction step, accumulator 12 and multiplier 13, as well as an element ШШ 14, with this threshold scheme entrance gate inii 1 and the input of the delay shift register 6 is not shown in the drawing.

The corrector works in the following manner. V

The received signal, converted into a sequence of i-coded code layers, is fed to the input of a digital delay line 1, which delays the signal for M ticks, and in parallel through a threshold circuit to the input of a shift register 6 with an average delay of N + M ticks. L is the size of the bottom of the combination of the received signal X, the name of the delay at the output of the T1-FLOW line 1, after the compensation of the components of intersymbol interference in the adder 2

7583L

arrives at the output of the corrector in the form

2-bit combination as a result of gating in gating element 3 with memorization. 2 - the bottom of the combination from the output of the gating element 3 with memory is fed to the summing input of the correction error determiner 5 and in parallel to the input of the amplitude and discriminator 4, containing logical circuits, by which the decision is made to which level (O or 1) is closest the corrected signal is located i.e. amplitude discriminator 4 provides an estimate for signal J.

Similarly, the threshold circuit, established between the input of the delay line 1 and the input of the shift register 6, provides an estimate of the input signal X c along with its sign Q | . The correction error determiner 5, forming the difference between the signal (and the QO estimate, gives a correction error bd along with the sign of 6.) In accordance with the accepted sign algorithm, to find the pulse response hj at the output of the corrector, multiply the sign of the correction error by the sprinkling mark O, taken with the corresponding delays. Such a multiplication of binary signals is realized in the modulator two modulator 8. The analysis shows that the delay of the sign of the error of the correction of 1 SAG by the required number of ticks is essential to refuse due to Hovhan posshok a, emogo carried out with input of the corrector, i.e. to use only delayed spreading receptacle $ 1 Commercially shift register 6.

Thus, the maximum rightness estimate of the corresponding reference of the reduced impulse response at the output of the corrector 5 is obtained by accumulating increments in the corresponding accumulator 12 of the SIL generator 7, and the increments are obtained by averaging with POM1191 reversible counter 10 a large number of products of the form

,, CD

formed by the adder 8 modulo 45 two formers 7 LSL.

. In accordance with expression (1), one of the inputs of each of the adders 8 modulo two of all formers 7 of the SMP is signified by an error sign 6 (5 from the output of the determinant 5 correction errors and the other input of the adder 8 modulo two is the sign of the corresponding parcel d1 taken from the output of the corresponding cell of the shift register 6. The inputs (addition and subtraction) of the reversible counter 10 receive pulses of the clock frequency P, which are passed by the corresponding element AND 9. At the beginning of the correction process, the contents of each of the reversible counters 10 and each From the accumulators 12 of all the formers 7, the SMP is set to the initial state by the signal N. (initial setting) .In order for the correct operation of the corrector, it is necessary to eliminate the overflow of any of the accumulators 12 of all the formers 7 of the SMP. the moment when the decoder 11 is triggered during the growth combined with the multiplier by the correction step. Accordingly, the contents of the corresponding accumulator 12 change to “6 or-8, where 8 is the correction step; With the help of the OR element 14, which combines the outputs of each of the decoder 11 increments combined with multipliers by the correction tag, of all the SMP drivers, the initial state of each of the reversible counters 10 of all the SMP drivers 7 is installed, if at least one of the decoders 11 increments fixes the overflow of any reversible counter 10, which increases the accuracy of the correction. From the output of accumulator 12, the Z-discharge of the combination of the corresponding count fj of the reduced output impulse response, taken at one of the inputs of the corresponding multiplier 13 of the SMF generator 7, is removed, and the other input is evaluated; parcels from the output of the corresponding cell of the shift register 6. The result of the multiplication enters the corresponding subtractive input of the adder 2. At the output of the adder 2, as a result of the correction of the components of the intersymbol interference, a sum in the form of V-Xo is formed. on the output of the corrector associated with the reading of the impulse response as e..o-, -and i U bj, the contents of each of the accumulators 12 of the formers 7 SMP in accordance with the iterative process of operation of the corrector changes until the signal about Correction errors, having at the output of the correction error 5, will not be equal to zero. Thus, the accuracy of the corrector is improved by erasing information about the old error of correction, when at least one of the reversible counters 10 reaches the counting boundary, in all reversible counters. The application of the proposed device allows to increase the accuracy of correction by eliminating a false set of impulse response counts and ensuring that the contents of each of the drives are independent of changes from the contents of other drives. The OR element, the combined output of all increment decoders, can be reduced by a factor of 3-4. capacity of each of the reversible counters.

Claims (1)

A CORRECTOR containing a shift register, shapers of a component of intersymbol interference, each of which consists of a series-connected adder modulo two, an element And, the second input of which is an input of clock pulses, a reversible counter, an increment decoder, a drive and a multiplier, and a digital line connected in series delays, the input of which is connected to the input of the shift register through the threshold circuit j adder, a gating element with memory and amplitude discriminator, the input and the output of which is connected respectively to the inputs of the correction error determinant, the output of which is connected to the first inputs of the adders modulo two, the second inputs of which are connected respectively to the outputs of the shift register and to the second inputs of the corresponding multipliers, the outputs of which are connected to the subtraction inputs of the adder, characterized in that that, in order to improve the accuracy of correction, an OR element is introduced, while the output of each increment decoder is connected to the corresponding input of the OR element, the output of which is connected to any inputs of reversible counters. > 1 1137583 2