SU736099A1 - Discrete frequency multiplier - Google Patents

Description

one

The invention relates to automation and computing, in particular, devices for multiplying the pulse frequency of a periodic signal.

A discrete frequency multiplier is known comprising a pulse shaper, a control unit, a frequency divider, a reference frequency generator, a key, a correction unit performed on the counter, a single-oscillator and AND elements, and a multiplication unit performed on the counters, the memory register and the AND and OR 1 elements .

The disadvantage of the device - ponit-. .. the accuracy of the multiplication of the pulse frequency.

The closest to the present invention is a discrete frequency multiplier that contains a switch, the signal input of which is connected to the frequency reference bus, the first control input is connected via the first pulse-to driver to the input of the frequency multipliers, and the first output is connected to the input of the control unit connected to the first output terminal inputs of zeroing two memory registers, the second output - to the first inputs of the i-elements of the first and second groups.

and the third output - to the installation inputs of the first counter and frequency divider and the second / control input of the switch connected by the second 5 output to the counting input of the frequency divider, the code output of which is connected to the BTopoNfi input of the AND elements of the first group connected to the information output of the first memory connected to the bits of the outputs to the corresponding control inputs of the digital-controlled line of the zadlerski, and the code output of the first counter connected to the counting

15 input with the output of the frequency divider overflow, connected to the second input of the elements AND of the second group, connected to the output of ind) by the memory input of the second memory register, output

20 of which is connected to the first input of the elements AND of the third group connected by the second input through the second pulse shaper with the output of the second counter connected by code

25 input to the output of elements of the third group, and the signal input of the digital-controlled delay line connected by the output with the device output is connected to the output of the second pulse formator, and the counting input

The second counter is connected to the reference frequency bus. The digitally controlled delay line in the prototype is made on n (where n is the number of control code bits) of parallel-connected circuits, each of which "contains the I element and the delay element" The outputs of the circuits are connected to the inputs of the output element OR, and the control inputs of the elements And connected to the outputs of the decoder. The switch is made on the trigger and two elements And 2.

The disadvantage of the device is the reduced accuracy of multiplying the pulse frequency of the periodic signals by a constant coefficient.

The purpose of the invention is to increase the accuracy of multiplication. ..

For this purpose, a discrete frequency multiplier containing a switch, the signal input of which is connected to the reference frequency bus, the first control input, is connected via the first pulse shaper to the input of the frequency to be multiplied, and the first output is connected to the input of the control unit connected to the inputs zeroing two memory registers, the second output - to the first inputs of the And elements, the first and second groups, and the third output -:; to the installation inputs of the first counter and frequency divider and the second control input of the switch connected to the second output with the counting. the input of the frequency divider, the code output of which is connected to the second input of the elements AND of the first group connected by the output to the information input of the first memory register connected by the bit outputs to the corresponding control inputs of the digital-controlled delay line, and the code output of the first counter connected by the counting input to the overflow output of the frequency divider is connected to the second input of the elements AND of the second group connected by the output to the input (the output input of the second memory regaster, the output of which is connected to the first the course of the elements of the third group connected by the second input through the second pulse shaper to the output of the second counter connected by a code input to the output of the elements AND of the third group, the switch, the delay element, the OR element and the output driver connected by the input to the first input of the OR element, per a) the control input of the additional switch and the output of the digital-controlled delay line connected by a signal input with the first output of the additional switch, the second output of which is connected to the c4eTHOtiy input of the second counter and the second input of the OR element connected

the third input with the start-up bus and the output connected via the delay element to the signal input of the additional switch, the second control input of which is connected to the output of the second trg of the pulse pulser.

In addition, the Digital Controlled Delay Line contains n delay elements, n OR elements and two groups of n AND elements (where n is the number of bits of the control code), with the output of each i-element OR (l $ i: Sn) connected by the first input with the output of the i-ro element And the first group and connected by the second input through the delay element to the output of the i-ro element And the second group, connected to the first inputs (i + l) -x elements And the first and second groups connected the second inputs to the control and inputs of the digital-controlled delay line, the first inputs of the first and the second And elements of both groups are connected to the signal input of the digitally controlled delay line, and the output of the nth element OR is connected to the output of the digitally controlled delay line.

The drawing shows a block diagram of a discrete frequency multiplier.

The device contains a frequency divider 1, the division factor of which is equal to the device multiplication factor K, the first counter 2, the first 3 and second 4 pulse shapers, the output shaper 5, the second counter 6, the first 7 and the second 8 memory registers, the first 9, the second 10 and the third 11 groups of elements AND, the control unit 12, digitally directing its 13 delay line 13, the main 14 and an additional 15 switch, the element 16 OR, the delay element 17,

The digital delay line 13 contains the elements 18 OR, the delay elements 19, the elements 20 AND of the first group and the elements 21 AND of the second group

The device works as follows.

Each input pulse is multiplied by frequency f. through the first driver 3, it enters the first control unit and the 1st input of the switch 14 and switches it to a state in which the reference frequency pulses SP) coming to the signal input of the switch pass only through its first output to the input of the control unit 12. During the arrival time in block 12, fon pulses in this block produce three signals in succession, the first of which flushes registers 7 and 8, the second signal taken from the second output of block 12 enters the first inputs of groups of elements 9 and 10, making My code from the divider 1 frequency in the register 7 memory and transfer

return code from counter 2 to 8 memory registers. The third signal, removed from the third output of block 12, sets in counter 2 all bits (except the younger one) to the unit state and writes a number equal to the frequency pulses passed to the block 12 input to the frequency divider 1. At the same time, the third signal of the switch 14 the second control input is set to a state in which the frequency pulses pass only through its second output to the input of the frequency divider 1.

Pulses from the output of divider 1, the frequency of which is equal to fpp / K, are sent to the counting input of counter 2. For one period Tj of the following multiplied frequency, the number of pulses equal to

N -,

where m is the number of frequency pulses

fon) remaining in the divider 1 by the end of the period T () Tdg, is the period of the pulse frequency.

However, due to the installation in the counter 2 of the pre-code, a number equal to NX 2 is recorded in it. This number after the next frequency pulse f% is received by the signal from the second output of block 12 is transferred in reverse code to register 8 (i.e. in memory register 8 sets the additional code number). At the same time, with the same signal from block 12 of frequency divider 1, the remainder of divider m is transferred to memory register 7.

 The multiplication process starts from the moment the pulse is applied, and starts on the device launch bus. This pulse (the corresponding connections on the blog are not. Shown) unlocks the group of elements 11 AND, as a result of which the additional code of the number is read from register 8 to the counter 6. This same pulse starts through element 16 OR enters the input of the delay element 17 having delay time equal to Tdr. At the output of the Element 17, a sequence of pulses occurs with a following frequency (these pulses come from the second output of the additional switch 15 to the counting input of counter 6 and the second input of element 16 OR). to the second input of a group of elements 11 I, having re-enumerated the additional code from register 8 to counter 6. The same signal from the output of the fop o of driver 4 is fed to the second control input

the switch 15, switching it to a position in which the pulses coming from the output of the delay element 17 to the signal input of this switch pass only to its first output, i.e. At the output of the delay element, a pulse passes from the first output of the switch 15 to the signal input of the digital-controlled line # - 13 delay.

Depending on the state of the bit size of the memory register 7 (the direct and inverse outputs of which are connected to the control inputs of the delay line 13), the pulse will be fed to the inputs of the elements 16 OR or the corresponding elements 20 through the corresponding elements 21 and elements 19 delays.

The delay time t on line 13 is defined by

- | rl,

where p is the digit of the control code, the receiving symbol

reading

or

five

t - is the delay time corresponding to the weight of the discharge.

The minimum value of the delay of the elements 19 is chosen equal and corresponds to a single state 0 of the youngest register register 7

(further th

etc).

Thus, if the residual number in divider 1 is equal to t, then the pulse at the output of line 13 relative to its signal input is

With delay - This impulse switches over the first control input switch 15 to its initial state (in which the pulses pass only to the second output of this switch) and passes through element 16 OR to the input of delay element 17, further operation of the device occurs as described above.

The repetition period of the pulses at the output of the output driver 5 is equal to

T n T - To tv Iaa-Ik

you % op to CT „„ K. to

on

or

b.– the proposed device allows to increase the multiplication accuracy by

5 reduce the error from the non-uniformity of the pulse sequence of the output sequence to the limit possible for discrete multipliers. This error is equal to 1 - under the condition that the filling error of divider 1 is ± one pulse of the reference frequency.

Claims (2)

1. The discrete frequency multiplier, containing the switch, the signal (whose input is connected to the reference frequency bus, the first control input is connected via the first pulse shaper to the input frequency and the first output is connected to the input of the control unit and connected to the zero output of the two memory registers by the first output, the second output to the first inputs elements of the first and second groups, and the third output - to the installation inputs of the first counter. and the frequency divider and the second control input of the switch connected by the second output to the counting input of the frequency divider, code output cat The first is connected to the second input of the elements AND of the first group connected by the output to the information input of the first memory register connected by the bit outputs to the corresponding control inputs of the digital-controlled delay line, and the code output of the first counter connected by the counting input to the overflow output of the frequency divider is connected to the second input of elements AND of the second group, connected by the output to the information input of the second memory register, the output of which is connected to the first input of elements AND of the third group, connected The second input through the second pulse shaper with the output of the second counter connected to the BETTER input to the output of elements AND of the third group, characterized in that, in order to improve the multiplication accuracy, a switch, a delay element, an OR element and an output driver connected to the input to the first input of the element OR, the first to the control input of the additional switch and the output ion g a digital-controlled delay line connected by a signal input to the first output of an additional switch, the second output of which is connected to the counting input of the second counter and the second input of the OR element connected by a third input to the start bus and connected to the output through the delay element to the signal input of the additional switch, the second control The input of which is connected to the output of the second pulse driver. 2. The multiplier according to claim 1, wherein the digitally controlled delay line contains n delay elements, n OR elements and two groups of n And elements (where n is the number of bits of the control code), with the output of each 1 th element OR () connected by the first input to the output of the i-ro element And the first group and connected by the second input through the i-th delay element to the output of the element And the second group is connected to the first inputs (i + l) -x elements AND the first and second groups, connected by the second inputs to the control inputs of the digital-controlled delay line, Rich first inputs of first and second members and both groups are connected to the signal input tsifroupravl emoy delay line, and an output of OR connected to the output tsifroupravl emoy delay line. Sources of information taken into account in the examination 1. USSR author's certificate 576658, cl. H 03 K 5/01, 1976. 2 "USSR Author's Certificate No. 544112, cl. H 03 K 5/01, 1975 (prototype),