SU840878A1

SU840878A1 - Binary-coded decimal "12222" code- to-serial code converter

Info

Publication number: SU840878A1
Application number: SU792814335A
Authority: SU
Inventors: Анатолий Иванович Журавлев
Original assignee: Рязанский Завод Счетно-Аналитических Ма-Шин
Priority date: 1979-08-28
Filing date: 1979-08-28
Publication date: 1981-06-23

Description

1one

Изобретение относитс к автоматике и вычислительной технике и мо сет быть использовано в устройствах дл преобразовани информации.The invention relates to automation and computing, and the model can be used in devices for information conversion.

Известен преобразователь параллельного двоично-дес тичного кода в унитарный код, содержащий регистр хранени кода, элемент И, элемент , ИЛИ и элементы задержки 1. A parallel binary-decimal code converter into a unitary code is known, comprising a code storage register, AND element, element, OR, and delay elements 1.

Недостаток этого преобразовател состоит в том, что применение фиксированных элементов задержки пои равномерном распределении импульсов в пачке выходного кода не позвол ет произвольно измен ть частоту следовани импульсов опроса.The disadvantage of this converter is that the use of fixed delay elements on the uniform distribution of pulses in the output code burst does not allow the random frequency of the polling pulses to be changed arbitrarily.

Наиболее близким к предлагаемому изобретению по технической сущности вл етс преобразователь двоичнодес тичного кода 12222 в последовательный код, содержащий входной регистр, группу элементов ИЛИ, группу элементов И, первые входы которы соединены с тактовым входом преобразовател , вторые входы соединены с пр м1лми выходами соответствующих элементов ИЛИ группы, первый и второй элементы ИЛИ, причем выходы элементов И группы соединены с первыми входами соответствующихThe closest to the invention according to the technical nature is a converter of binary code 12222 into a serial code containing an input register, a group of elements OR, a group of elements AND, the first inputs of which are connected to the clock input of the converter, the second inputs are connected to the direct outputs of the corresponding elements OR groups, the first and second elements OR, and the outputs of the elements AND groups are connected to the first inputs of the corresponding

элементов ИЛИ группы и соответствующими входами второго э.п-емента ИЛИ, первый вход первого элемента ИЛИ соединен с выходом первого элемента И группы, а выход перврго элемента ИЛИ вл етс информационным .выходом преобразовател , инверсный выход i-ro элемента ИЛИ группы ( (п-1)), где п число разр дов преобразуемого кода соединен с третьим входом (i+l)-oro элемента. И группы, единичные выходы разр дов регистра соединены со вторыми входами соответ:ствующих элементов ИЛИ группы 2.the elements of the OR group and the corresponding inputs of the second OR element, the first input of the first element OR is connected to the output of the first element AND of the group, and the output of the first element OR is the information output of the converter, the inverse output of the i-ro element OR of the group (( -1)), where n is the number of bits of the code being converted is connected to the third input of the (i + l) -oro element. And the groups, single outputs of the register bits are connected to the second inputs of the corresponding: OR elements of group 2.

Недостаток известного преобразовател состоит в сложности схемного решени , заключающегос в необходимости введени дополните.г1ьной группы элементов И и управл ющего триггера.The disadvantage of the known converter consists in the complexity of the circuit solution, which consists in the necessity of introducing an additional group of AND elements and a control trigger.

0 Кроме того, существенным недостатком вл етс необходимость жесткой фиксации разр дов кода 2222 при заполнении регистра, в зависимости от значени кода. Например, дл кода,0 In addition, a significant drawback is the need for rigidly fixing the bits of code 2222 when the register is filled, depending on the value of the code. For example, for a code

5 соответствующего дес тичному числу 4, необходимо распределить информацию в виде 01100, где крайний левый5 corresponding to the decimal number 4, it is necessary to distribute information in the form of 01100, where the leftmost

Claims

bit corresponds to weight 1, i.e. the register is filled permanently, from left - to the right. At the same time, in many cases, the code is written in the form 00011. This limitation is absent in the proposed scheme. The purpose of the invention is to simplify the device and expand its functionality, which consists in providing the ability to control the polling frequency. The goal is achieved by the fact that a binary code converter 12222 into a serial code containing an input register, a group of elements OR, a group of elements AND, the first inputs of which are connected to the clock input of the converter, the second inputs are connected to the direct outputs of the corresponding elements OR of the group, the first and second elements OR, the outputs of the elements AND of the group are connected to the first inputs of the corresponding elements of the OR group and the corresponding inputs of the second element OR, the first input of the first element OR the output of the first element AND of the group is output, and the output of the first element OR is the information output of the converter, the inverse output of the i-ro element OR of the group (f (nl) J, where the code of the transformed code is coi, is dinene with the third input The (1 + 1) -th element of the AND group, the unit outputs of the register bits are connected to the second inputs of the corresponding OR elements of the group, the element I is included, the direct input of which is connected to the single trigger output of the first time row of the register, the inverse input of with the output of the second element OR, the input is set The trigger unit of the first bit of the register and the second input of the first element OR, the direct output of the 1st element OR of the group are connected to the third input (iH) -oro of the element OR group, the outputs of the AND elements of the group are connected to the inputs of the settings of the corresponding bits the registry, the direct output of the nth OR element of the group is the output of the conversion end. The drawing shows a block converter circuit. The sampler contains an input register 1 consisting of triggers, a group of elements OR 2, a group of elements IZ, the first and second element OR 4 AND 5, an additional element AND 6, input 7 of the transmitter interrogation, information output 8 of the converter, and signal output 9 of the converter. The Converter operates as follows. If the left significant trigger with a weight of 2 input register 1 is recorded, then when the first polling pulse arrives at input 7 at the second input of the AND element of the group of the corresponding digit, the output. of the OR 4 element, a single impulse is formed. It is fed to the information output 8. At the same time, the impulse from the output of the corresponding element AND of group 3 embraces the interrogated register trigger with a weight of 2, the impulse from the output of the element OR 5. sets in 1 the trigger weight, input register and enters the inverse input element And b,. preventing false triggering of the element AND 3 groups of discharge with weight. After the end of the interrogation pulse, all elements of the 3 groups of bits with a weight at the third input are closed by the inhibitory potential. When the second polling pulse arrives, the last one passes through the AND 3 group of the bit with the weight and through the OR 4 element to the information output 8. At the same time, the trigger with weight i is zeroed. Thus, each significant register bit with a weight of 2 corresponds to two pulses at the output of the information bus 8. Next, the next element And 3 corresponding to the closest significant digit with a weight of 2 is polled in the same way. The output code is issued in the form of a burst of pulses uniformly distributed in time. After polling the last element AND 3 of the group, the input register takes zero values in all bits and at the output of the right extreme element. OR group 2, a signal is generated. A conversion end that is fed directly to the signal output 9 of the converter. Thus, the structure of the device allows, with a small amount of equipment, to obtain at the output a sequential code in the form of a burst of pulses uniformly distributed in time for any distribution of information in significant bits with a weight of 2 input registers. The invention of the Converter binary-decimal code 12222 in serial, a code containing the input register, a group of elements OR, a group of elements AND, the first inputs of which are connected to the clock input of the converter, the second inputs are connected to the direct outputs of the corresponding elements of OR group, the first and second the OR elements, the outputs of the AND elements of the group are connected to the first inputs of the corresponding OR elements of the group and the corresponding inputs of the second OR element, the first input of the first OR element is connected to the output n The first element of the AND group, and the output of the first element OR is the information output of the converter, the inverse output of the i-oro element of the OR group (f (p-1)), where n is the number of bits of the code to be converted to the third input (ifl) -th element AND group, the single outputs of the register bits are connected to the second inputs of the corresponding elements OR group, characterized in that, in order to simplify the converter and extend the functionality that includes the ability to control the polling frequency, it includes the input of which is connected to the unit output of the first digit register register, the inverse input is connected to the output of the second element OR, the installation input of the trigger unit of the first register bit and the second input of the first element OR, the direct output of the i-oro element OR group is connected to the third input (ifl ) -th element OR group, the outputs of elements AND group are connected to the installation inputs zero of the corresponding register bits, the direct output of the n-th element OR group is the output of the conversion end. Sources of information taken into account during the examination 1. USSR author's certificate on application 2551548/24, class C. 06 F 5/04, 1977.

2. USSR author's certificate according to application No. 2671067/24, class C. 06 F 5/04, 1978.