SU840819A1 - Multichannel device for tolerance checking of parameters - Google Patents

Description

The invention relates to computational and instrumentation technology and can be used to control processes in various technological objects, such as turbo-generators of power plants. Multichannel devices for tolerance control are known, containing a series-connected controlled multichannel scale converter, analog adders, direct analog-code converters, a measured information output block, a code analog counterpart for all canons, and a calculating block. The disadvantages of such a multichannel device for tolerance control are its complexity, due to the presence of a large number of converters analog-code and augment adders, and low accuracy of measurements of object parameters since the comparison operation performs on an analog adder. It is also known to have a multi-channel device for tolerance controller JЯ containing sensors, functional converters, a source of reference signals, a switch, an analog-digital converter, a set register, a control result register, a control result processing unit, a recording unit, a display unit, an audible alarm unit and a control unit R2. The disadvantages of this multi-channel tolerance control device are low speed and relatively low accuracy, which are caused by the presence of a switch. The closest to the technical essence of the invention is a device for tolerance control, containing a one-shot, serially connected display unit, a comparison unit and a pulse distributor, the second output of which is connected to the single-input input, the output of which is connected to the second input of the comparison unit, as well as a pulse generator, connected by the first output to the input of the registration unit, the other inputs of which are connected to the output of the one-shot and the output of the dynamic register, respectively, adder / plug The first output to the input of the dynamic register and the output of the output to the first input of the first element I, the output of which is connected to the input of the pulse distributor, two triggers, the outputs of which are connected respectively to the first inputs of the second and third elements I, connected by the second inputs to the corresponding signals the inputs of the unit are set, the elements or connected by the inputs to the outputs of the dynamic register of the second and third elements AND, respectively, and the delay element connected by the output to the first input of the adder and the input to ervym inputs of the first and second flip-flops, a second input of the first AND gate and the second output of the pulse generator, the second input of the adder connected to the output of OR element,

The disadvantages of this device are its limited functionality, due to the single-channel control and the complexity of implementation in the case of multi-channel control, since hardware costs increase in proportion to the number of control channels.

The purpose of the invention is to simplify the device,.

The goal is achieved by the fact that a multichannel device for tolerance control of parameters, containing a pulse generator, connected to the first input of the recording unit by a first output through successively connected delay elements, an adder and the first register whose output is connected to the first input of the first RSHI element, the second generator output pulses are connected to the second input of the registration unit and to the input of the setting unit, the first and second outputs of which are connected to the first inputs of the first and second elements, respectively, single outputs with the second and third inputs of the first element OR, and the second inputs with outputs of the first and second triggers respectively, the first inputs of which are connected to the first output of the pulse generator, and in each channel a single vibrator and the third element sequentially connected, the first pulse distributor, block the comparison and the display unit, the second input of the comparison unit is connected to the output of the single-Vibrator and to one of the third inputs of the registration unit, the input of the one-vibrator is connected to the second output of the first distributor pulses, and the first inputs of the third elements and the second input of the adder, additionally entered the second register, the second pulse distributor and elementa OR, the outputs of the second pulse distributor are connected to the second inputs of the third elements AND, and the input to the first output of the pulse generator, input the second register

and the output with the second input of the adder, the inputs of the second element OR are connected to the second outputs of the first distribute the pulse flow, and the output to the second input of the first trigger, the inputs of the third element OR are connected to the third output of the first pulse distributors, and the output with the second input of the second trigger . The drawing shows a structural diagram of a multichannel device for the tolerance control of parameters. The device supports radio frequency vibrators.

I, generator 2, pulses, unit 3 of settings, units 4 of comparison, blocks 5 of indication, block 6 of registration, first register 7, adder 8, distributor 9 of pulses, two triggers 10 and

II, delay element 12, element OR 13, three elements AND 14-16, two elements OR 17 and 18, the second distributor 19 pulses second register 2

The device works as follows.

Single-oscillators 1 convert input monitored parameters x, i 1,2, ... N, where N is the number of input channels, into pulse signals, the duration of which is proportional to the magnitude of the input signal.

The pulse generator 2 produces clock pulses at the first output, with a frequency f, and pulses at the second output - at a frequency f / n, where n is the number of binary bits of the dynamic register 7.

The distributor 19 pulses from the output signals, the generator 2 pulses forms on its N outputs AND pulse sequences, acting with a frequency of f / n-N.

Unit 3 of settings generates two clock sequences of setpoint pulses corresponding to the lower tolerance limit Hz and the tolerance field Xg - Hz, where x is the upper tolerance limit.

At the first output of block 3 of settings, N consecutive binary codes 2-Xc are sequentially generated, I in 1.2, ... N, where n is the number of bits of the first register 7, N is the number of input channels.

At the second output of block 3 of settings, N consecutive binary codes 2 - (x "), t 1,2, ... N are sequentially generated.

The binary codes of the settings 2 - x and 2 - (xg - hcc), I "1,2 ... N, arrive after the order of the order of numbers, it is important from the discharges, to the second inputs of the And 15 and 16 / elements, respectively.

The first register 7 contains n binary bits and can store a binary setpoint code. The second register 20 contains (N-l) n binary bits and can store N - 1 binary codes.

settings. The sequential connection of registers 7 and 20 through the element OR 13 forms a dynamic register containing - N binary layers in n bits each.

Consistent. The connection of registers 7 and 20 with adder 8 forms a binary counter, sequentially performing in N Slovakia an independent counting of synchronizing pulses of the second generator output of 2 pulses, which, through the delay element .12, arrive at the first input of the adder 8 at the moments of the least significant bit of each word.

As a result of continuous independent counting in N words over certain periods of time, counter overflows occur, which are generated as transfer signals from the n-th ra: era of each word at the second output of the adder 8.

The distributor 19 controls, using elements AND 14, the distribution of transfer pulses from the n-th bits of each word over N parallel channels in such a way that the overflow pulse: in the first word goes to the input of the first channel distributor 9, the overflow pulse in the second word goes to the input of the distributor 9 of the second channel and. etc.

The distributors 9 of each channel, in turn, perform the distribution of the transfer pulses and the n-th bit of the corresponding word across the three outputs.

- The operation of the device operating in continuous generation mode at the outputs of the distributors 9 pulse signals, consider, for example, from the moment of generation at the second output of the distributor 9 of the first channel of the output pulse, which starts the single-channel 1 channel and through the OR element 17 sets the second input trigger condition.

A single-channel 1 of the first channel, after being triggered by a triggering pulse, produces, at the output, im-. pulse signal, the duration of which is proportional to the magnitude of the input signal on the first channel.

The trigger 10, after setting it to a single state, identifies the element 15.

The binary code of the setpoint on the first channel 2 - x from the first output, the block of settings 3 through the elements 15 and OR 13 enters the input of the register 20 and writes in it in the first word the initial BINARY code corresponding to the lower tolerance limit for the first channel,

After the delay time in register 20, the serial binary code of the setpoint on the first channel 2 - Hz is received sequentially in time.

starting with the least significant bit, to the second input of the adder 8, to the first input of which the output of the delay element 12 is the synchronizing impulse pattern of the bit.

As a result of the summation of the sugator 8, the binary code 2 - Hz is incremented by one and the new binary code 2 - x ". + 1 from the first output of the adder 8 is written to the register 7.

After passing the binary code

0 2 - Hz through the element 15 And the trigger 10 is reset on the first input to the zero state by a pulse of the second output of the generator 2.

After the trigger 10 is set to the zero state, the AND 15 element is closed and the arrival of the binary setpoint code at the input of the OR 13 element is terminated.

The binary code in the first word 2 0 - х „I h - 1 from the output of the register 7 through the element OR 13. is written to the register 20, from the output of which, lowering the delay time of the register 20, goes to; the second input of the adder 8.

The adder 8 will again increment the binary code in the first word by one and the result of the summation 2 - x + 2 is written to register 7.

This continues until, in time, the summation in the first word

0 at the output of the adder 8 does not follow the transfer pulse from the nth bit. This occurs after an interval, the time Hz n N / f after the launch of the one-channel one-shot 1. In that

5 a moment of time at the first output of the distributor 19 acts a pulse that unlocks the first channel element I 14 of the first channel, through which the overflow pulse from the second output

0 adder 8 is fed to the input of the distributor 9 of the first channel. The distribution: the carrier 9 of the first channel transmits the input pulse to its third output and terminates the signal on the first bus of the first output, which is 5 at the time the pulse is generated at the second output.

Thus, on the first bus of the first output of the distributor 9 of the first channel, a pulse is produced whose duration is equal to the lower tolerance limit on the first channel.

. The signal from the first output of the distributor 9 is fed to the first input of the comparator unit.

If the monitored parameter on the first channel is x less than the lower 11th tolerance page, then the duration

0 pulse at the output of the one-shot 1 will be less than the duration of the pulse at the first output of the distributor 9.

Claims (2)

In this case, a pulse signal with a duration (x, - x) nM / which is received in display unit 5 is generated at the first output of the comparison unit 4 and triggers the alarm element at the output of the monitored parameter on the first channel within the lower tolerance limit. If the monitored parameter on the first channel is greater than the lower tolerance limit, then the pulse duration at the output of the one-shot 1 is longer than the pulse duration on the first bus of the first output of the distributor 9, and there is no signal at the first output of the block compared to 4. . I After the first overflow in the first word, the transfer signal from the nth. the bit of the first word comes from the third input of the switch 9 of the first channel through the element OR 18 to the second input of the trigger 11, setting it to one. A trigger 11 triggers element I 16. A binary setpoint code for the tolerance field of the first channel 2 - (xg XH) about the second output of block 3 of settings via elements AND 16, OR 13 enters the input register 20, where it is written in the first word. After all the binary code 2 - (y - t) bits pass through the AND 16 element, the trigger 11 is reset to the zero state by the second output pulse of the generator 2. The binary counter formed by the serial connection of register 7 and 20 and the adder 8 performs in the first In a word, the low-order pulses that come from the output of delay element 12, starting with the start code 2 - (Xn - x). After a time interval (xj, - x) n H / f after the first overflow, the second overflow occurs in the first word and the transfer signal from the nth order appears at the second output of the adder 8. the discharge of the first word, which is via the element I 14 of the first channel open by the signal of the first output of the distributor 19, passes to the input of the distributor 9 of the first channel. As a result, a signal appears on the second bus of the first output of the distributor 9, which acts until the next (third) overflow of the first word. If the monitored parameter x is greater than the upper tolerance limit Xd, then the pulse at the output of the one-cycle 1 acts for some time after the second overflow of the first word. The coincidence of the trailing edge of the output pulse of the one-shot 1 with the leading edge of the pulse on the second bus of the first output of the distributor 9 is highlighted by the comparison unit 4, at the second output of which a pulse of duration (X - xg) n N / f is formed. The output pulse of the comparison unit 4 enters the display unit and causes the alarm element 0 to exit the monitored parameter through the first channel beyond the upper tolerance limit. If the monitored parameter on the first channel is less than the upper tolerance limit, then the signal at the second output of comparison unit 4 is absent, since the pulse at the output of the one-shot 1 Finishes before the pulse starts on the second bus of the first output of the distributor 9. After the second overflow of the first word, the binary counter, formed by registers 7, 20 and adder 8, performs counting in the first word from a zero starting code. Therefore, an overflow of the first word trap occurs after a time interval .M / f after the second overflow. The third overflow in the first word, coming from the second output of the adder 8 through the element and 14 of the first channel to the input of the distributor 9 of the first channel, stops the signal on the second bus of the first output of the distributor 9 and leads to the generation of a pulse at its second output. A pulse from the second output of the distributor 9 of the first channel starts the one-channel one-shot 1 of the first channel and sets the trigger 10 to one state through the element OR 17. The cycle of operation of the device on the first channel is repeated in a similar way. In the same way, tolerance control is performed on all other channels. The binary counter formed by the registers 7, 20 and the adder 8 performs independent counting in all words, and the pulses — transfers from the nth digit of each word, formed at the second output of the adder 8, are distributed by the distributor 19 to the corresponding channel at the input of the corresponding distributor 9. The presence of an additional register 20 and additional elements OR 17 18 ensures that the binary codes of the settings of the lower limit allow the tolerance field to be written independently for each monitored parameter, which allows the use of a multichannel Noe tolerance control apparatus different physical nature to know various parameters Cheney E tolerance limits. The device, in addition to the qualitative estimates of the monitored parameters, performs quantitative registration of deviations from the lower and upper limits of the Tolerance for each monitored parameter separately. The quantitative estimate is recorded by the registration unit b after the termination of the output pulse of the one-channel 1 of the corresponding channel by reading the binary code from the output of the register 7 using the synchronization signals of the pulse generator 2. If the i-ro channel parameter being monitored is less than the lower tolerance limit for this channel, then at the moment the output pulse of the one-vibrator 1 i-ro channel in register 7 is terminated, the binary code (x), i.e. additional code of negative deviation of the monitored parameter on the j-th channel from the lower bound. Tolerance values Хц. . If the monitored parameter on the i-th channel is greater than the upper tolerance limit, then at the moment of the end of the output of the one-vibrator 1 i-ro channel, register 7 contains the binary code of the value x - Xg. i.e. direct code of the positive deviation of the monitored parameter on i mk ka. channel from the upper tolerance limit xj, -. Quantitative estimates of deviations from the upper and lower limits of tolerance for each controlled channel can be displayed on punched tape (punched card), digital printing, digital display and issued to the controlling computer. The technical advantages of the proposed multi-channel device for tolerance control consist in its simplification. Compared with the known device, the hardware costs of which grow in proportion to the number of input channels M, in the proposed device, instead of the N sum 1/1 device, only one is used, instead of the N register, two registers are required, the hardware costs of which in the case of their realization on the delay line or ultrasonic) does not depend on the number of bits, since when the capacitance of the register changes, only the delay time or the frequency of the clock pulses changes. The remaining additional costs of the proposed device (two elements OR 17-18 and an additional distributor 19 pulses) are lower than the corresponding additional costs of the known (2n flip-flops, 2N elements AND, N elements OR). Thus, the hardware costs are reduced by no less than an N-1 adder and N-2 registers, where N is the number of parallel input channels. Invention Multi-channel device for tolerance control of parameters, a pulse generator order connected by the first output to the first input the registration unit through a serially connected delay element, an adder and the first register, the output of which is connected to the first input of the first OR element, the second output of the pulse generator is connected to the second input of the registration unit and about the input of the setting block, the first and second outputs of which are connected to the first inputs of the first and second elements I, respectively, connected by the outputs with the third inputs of the first element —OR, and the second inputs from the output of the first and second triggers, respectively, the first inputs of which are connected to the first output the pulse generator and in each channel the single and serially connected third element I, the first pulse distributor, the comparator unit and the display unit, the second input of the comparator unit is connected to the output of RATOR and one of the third inputs of the registration unit, the one-shot input is connected to the second output of the first distributor, pulses, and the first inputs of the third I elements to the second input of the adder, characterized in that, in order to simplify the device, the second register, the second pulse distributor and OR elements, the outputs of the second pulse distributor are connected to the second inputs of the third AND elements, and the input to the first output of the pulse generator, the second register input is connected to the output of the first OR element, and the output from the second th input of the adder, in: moves the second OR gate connected to the second inputs of the first pulse distributor, and the output - to the second input of the first flip-flop, the inputs of the third OR gate connected to the third output of the first pulse valves, and an output - to a second input of the second flip-flop. Sources of information taken into account during the examination 1. USSR author's certificate No. 501369 / 18-24, cl. G 06 F 15 / 46,1978. 2. The copyright certificate of the USSR 607190 / 18-24, cl. G 05 B 23/02, 1978.. 3, USSR Author's Certificate in Application No. 2683265 / 18-24, cl. G 06 F 15/46, 1978 (prototype) Channel 1 Kohoaf