SU736093A1 - Decimal number comparing arrangement - Google Patents

Description

The invention relates to automation and computer technology and can be used in the implementation of computer hardware and automatic control and monitoring systems.

A device for comparing decimal numbers is known, containing counters, elements AND, OR, NOT and providing sequential bitwise comparison of numbers between themselves 1.

The disadvantage of this device is its low speed.

The closest technical solution to the present invention is a device for comparing decimal numbers, containing two registers, inputs associated with the output of the element I, and outputs with inputs of the memory elements of the corresponding number and inputs of the corresponding memory elements of the number compared with it, the control unit interrogation, the inputs connected to the outputs of the memory elements, the other outputs of which are connected to the display unit, the outputs to the interrogation inputs of the memory elements, and the control unit whose input is connected to the input of the element And, output to another input of the polling control unit and to the input of the element 2.

A disadvantage of this device is its complexity.

The purpose of the invention is to simplify the device.

The set; 1b is achieved by the fact that in the D1l device the comparison of decimal numbers, containing two n-bit binary-decimal registers, the control node, 2n memory elements, the comparison circuit, the And element and the display node, and the information inputs of the device are connected with inputs of binary-decimal registers, the input of clock signals is connected to the human input of the element I, the output of which is connected to the control inputs of the binary-decimal registers and to the information input of the control node whose output is connected to the second input of the element And the comparison circuit and with a control input, the outputs of which are connected to the inputs of the indication node, the output overflows. of each i-th decade, where i, ..., p of the first binary-decimal register is connected to the information input of the memory element and the control input of (n + i) ro of the memory element, the overflow output of each i-th decade of the second binary-decimal register is connected to the information input. (n + i) -ro. the memory element and to the control input of the 1st memory element, the outputs of the memory elements are connected to the inputs of the comparison circuit. The drawing shows a block diagram of the device. The device contains binary-decimal registers 1, 2, the elements 3 ,, For,. . ., 3, 3 „„. memory, comparison circuit, control unit 5, element b & b, display unit 7, informatic interface inputs 8.9, input 10 clock signals, c. The device works as follows. When comparing the numbers A and B among themselves, they are written in binary-decimal registers 1 and 2 in the initial state by information inputs 8 and 9. In the control node 5, each memory element 3 is in the zero state. The element 6 and 6 to the input of each decimal bit of the binary-decimal registers 1, 2 and to the input of the node 5 control also simultaneously receives a sequence of clock signals at the input 10 clock signals d. Each decade of binary-decimal registers 1 and 2 and control unit 5 are filled before overflow. At the same time, a decade with any decimal number of one number larger in absolute value overflows before a decade of the same order, but with a decimal number less than the absolute value of another number. For example, if in the i-th decade of binary-decimal registers 1 and 2, the digits aj of the number A and the bit in are written respectively; numbers B, where a- | and B | - any decimal digits of the same order of numbers A being compared with each other, and if in the past the i-a decade of the binary-part register 1 overflowed with the decimal bit aj written into it, since to overflow it to its input fewer filling pulses need to be supplied than to fill the decade of a binary-decimal register 2 and a decimal digit of Bj. Consequently, an overflow pulse at the output of a decade with any large PS the absolute value of the decimal digit of one of the compared numbers appears earlier than the overflow pulse at the output of a decade of the same order, but with a smaller absolute value of the decimal time: of the compared numbers, the overflow pulse with the output of the 1st decade of the binary-decimal register 1 with any large absolute value of the decimal digit of one number enters the information input of the corresponding i-th memory element and sets it to individual state. The same overflow pulse is fed to the input of the control-5 (n + i) -ro memory element and prohibits the passage of the overflow pulse from the binary-decimal register 2. In case of equality of the compared decimal digits, both the binary decade overflow simultaneously and overflow pulses are passed to the corresponding memory elements. Thus, after the termination of the comparison of decimal digits of the same order of the number A and B in registers 1 and 2, the results of the comparison in decades are recorded in the memory elements. The outcome of the above arguments, in the case of comparing the numbers A and B with parallel filling of the binary-decimal registers 1 and 2, is simultaneously bitwise compared to each other in,,. . . but,. where a, b are the highest decimal digits of the numbers being compared; the i-th decimal digits of the compared numbers; lower decimal times of the numbers being compared. The binary number comparison scheme 4 compares binary bits of the same order and, on command from the control node 5, outputs one of the commands More, Less, Equal and the command End of Comparison to the display node 7, since in the binary decade of the node 5 control In the initial state, the number O is written, then this decade determines the maximum filling time for binary-decimal registers 1 and 2 before overflow. Therefore, if at the output of the control unit 5 there appears an overflow pulse p going to the binary number comparison circuit 4 and to the input of the element 6, then all the decades of the binary-decimal registers 1 and 2 are filled before the overflow. An overflow pulse from the control unit 5 prohibits the passage of filling pulses through the element b and b and gives permission to indicate the result of the comparison. The comparison time is determined by the frequency of arrival of the filling pulses and does not depend on the size of the compared numbers. The device contains fewer nodes, and instead of a polling control node and a result formation node, a simpler node is used.

Claims (2)

1. USSR author's certificate No. 263278, cl. G 06 F 7/00, 01.20.69. 2. USSR author's certificate 0 No. 394778, cl. G 06 F 7/04, 10/18/71 (prototype).