SU570053A1 - Divider - Google Patents

Description

one

The invention relates to a digital technique n technology can be used in the construction of specialized clean gels n devices.

There are known devices for dividing, which allow us to obtain the whole part of the quotient or

Fractional CHETTs 1

The closest technical solution to the invention is a device containing a pulse generator, a divisible counter, a bluff determination of the end of the division, a register of bodies, a counter, elements AND, the first element outputs of which are connected to the bit outputs of the register of the divider, the second inputs of the elements AND are connected to corresponding outputs of the counter, the input of which is connected to the output of the pulse generator {2.

Both of these devices have low accuracy when performing division.

The aim of the invention is to improve the accuracy of the device.

This is achieved due to the fact that the device includes the element OR, the switch, the decoder, the counter, the elements AND

the delay element, the first input of which is connected to the first inputs of the additional elements AND, to the input of the Okrk: dividing unit, to the first output of the switch and to the control output of the counter, the first input of the switch is connected to the output of the element OR, whose inputs are connected to the outputs of the elements AND , the second entrance to the comm; This device is connected to the output of the decoder, the input of which is connected to the output of the divisible counter, whose input is connected to the second output of the switch and to the input of the additional counter, the control input of which is connected to the output of the delayed element, the second output of which is connected to the output of the delayed Yes, the counter, the bits of the additional counter are connected to the second inputs of the additional And elements, the outputs of which are connected to the corresponding bit inputs of the divisible counter.

The drawing shows a diagram of the device. The device for dividing includes a pulse generator 1, counters 2 and 3, divider register 4, elements AND 5 and 6, element OR 7, divisible counter 8, decoder 9, switch 10, delay element: 11, block 12 determining the end of division, output 13 devices. The device works as follows. Before divide division, divider 4 register contains divider value in binary code, divisor counter 8 contains divisible value in binary-ten code, counter 3 is zero, switch 10 is in open state, at which the output of the OR element is connected to inputs , the counter of the divisible 8 and the counter 3, the counter 2 is in the initial state. When the device is operating, the number of pulses arriving from the last P - bit of the counter 2 will be less than 02 times the number of pulses appearing from (n - k) to the corresponding hits element and 5 for one Other time intervals. The divider value recorded in the divider 4 register in binary code determines the state of the elements AND, therefore each pulse received from the output of the last bit of the counter 2 at output 13 corresponds to m pulses at the output of the element OR 7, where m is the value of the divider , “Recorded in the register of the divider 4. Pulses from the output of the element OR 7 arrive through the switch 10 to the counts of the divisible counter 8 and the generator. 3. Every nt“ pulses coming from the output of the element OR 7 to the output 13, one pulse passes; ; the value of the dividend recorded in the counter of the dividend 8 decreases zcc by m one, and the value of the remainder contained in the counter 3 varies from m to zero, since each pulse arriving at the output 13 also goes through the delay element 11 . Objectives of the counter 3. In order to avoid the simultaneous arrival of pulses on the counting and zeroing inputs of counter 3, which occurs at odd divider values, the delay time of the delay element 11 must be longer than the duration of the net pulse. If the value of the divisor is a multiple of the value. the last pulse to the output 13 and to the input of the delay element 11 arrives simultaneously with the moment of the onset of the zero state of the counter of the dividend 8 (with odd divider values) or immediately after the zero state of the counter 8 {with even values of the divider) and the time interval equal to the delay time of the element 11, zeroed the counter 3. Thus, at multiple divisor and divisible values, the remainder will be equal to zero. In the case of non-multiple values of the divider and the dividend at the moment of the zero state of the counter 8, the value of the first remainder will be recorded in the counter 3. The zero state of the divisible counter 8 is fixed by the decoder 9, which switches the switch 10. In this state, the switch 10 connects the output of the OR element 7 to the control inputs of the AND 6 elements and the first pulse from the output of the OR element 7 transfers the residual value from the counter 3 to divisible counter 8. The balance is transferred to this counter by a decimal shift so that the value of the remainder multiplied by 1 ° is overwritten by the dividend 8 counter. At the same time, the residual rewrite pulse enters the installation inputs of the counter 2 and sets it to the initial state, and also through the delay element 11 enters the converging inputs of the counter 3 and. sets it to zero. To correctly transfer the remainder to the divisible 8 counter, it is necessary for the rewrite pulse to arrive at the zero inputs of the counter 3 after the remainder of the remainder is transferred to the divisible 8 counter, which is reached by delaying the pulse using delay element 11 for a time longer than the pulse. During the time from the beginning of the division to the arrival of the first rewriting pulse, the output 13 will receive a number of pulses equal to the value of the whole part of the quotient. As soon as the first remainder has been rewritten into the counter of the divisible 8, the decoder 9 and, therefore, the switch Yu is returned to its original state. This is followed by analogous division cycles of previous residues multiplied by 10 by a divisor with the definition of subsequent residues. Between the arrivals of rewriting pulses at output 13, a number of pulses passes, equal to the value of the next decimal place. If, after the next rewrite pulse arrives, the zero value of the remainder is written to the divisible counter 8, the switch 10 remains in the closed state and the pulses from the output of the OR element 7 are passed to the counter insulating inputs, so that when the divider value is set, no output pulses go to output 13. The device is suitable for dividing two numbers at any ratio. Thus, the introduction of new elements and connections in the proposed device allows division to be performed with greater accuracy than with previously known devices.