SU1016845A1 - Device for measuring coefficient of grouping errows in discrete communication channel - Google Patents

Abstract

A DEVICE TO MEASURE THE GROUPING INDICATOR ERROR IN A DISCRETE COMMUNICATION CHANNEL, containing a series connected phase unit, whose input is the signal input of the device, a reference signal sensor and a comparison unit, the second input of which is connected to the input of the phase unit, the operation mode switch first the input of which is the input of clock pulses, the first divider, the first trigger and the first counter of the distorted blocks, the time counter, the error counter, the decoder, the control the trigger trigger, the shift register, the display unit, and the first and second elements AND, which are distinguished by the fact that, in order to improve the measurement accuracy, dividers from the second to –I are introduced into it, triggers from the second to –I; counters of distorted blocks with r-th, f + l multiplexers of counters, common multiplexer, computing unit, control pulse generator, first, second and third elements OR, key, additional switch, first, second and third counters of pulses, sensor control constants, a memory unit, an additional shift register, a signal combining unit, and an end-of-turn indicator, the output of the comparison unit being connected to the second input of the operating mode switch, the first output of which is connected to the combined inputs of dividers and the input of the time counter, the output of which is connected to the input of the generator of control pulses, the installation input of the control trigger and the control input of the operating mode switch, the second output of which is connected to the input of the error counter and the integrated installation inputs of the trigger, a reset input and output of each of which are connected respectively with .out. the house of the corresponding divider and the input of the corresponding counter of distorted blocks, the output of each of the co-§ and the error counter output are connected to the input of the corresponding counter multiplexer, whose outputs are connected to the corresponding inputs, a common multiplexer whose outputs are connected to the corresponding decoder inputs the outputs of which are connected to the corresponding inputs of the computing unit, the outputs of which are connected to the corresponding inputs of the display unit, the first output of the generator 0: 1 of the control torus and pulses through the switch eo connected to the input of the first pulse counter, outputs kotorogo.soedineny 4 :: combined with N inputs of multiplexers sootvetstvukltsimi counters ,. and the second output of the control pulse generator is connected to the clock inputs of the shift register and the additional shift register and to the reset input of the control trigger, the output of which through the first OR element is connected to the write input of the shift register, the output of which is connected to the combined first inputs of the first and second elements AND and with the addition input of the computing unit, the corresponding inputs of which are connected to the outputs of the signal combining unit, the inputs of which are connected to the corresponding output

Description

of the memory block and with the outputs of the corresponding bits of the shift register and the additional shift register / output and the recording input of which are connected respectively to the input of the end of calculation indicator and to the outputs of the first element I, the second input of which is connected to the direct output of the second pulse counter, inverse exit and entry. which are connected respectively to the second input of the second element AND, the output of which is connected to the second input of the first OR element, and to the output of the ninth digit of the shift register, the outputs of the second and fourth bits of which are connected to the first and second inputs of the second OR element, the output of which is connected with the first control input of the key, the second control input of which is connected to the output of the third OR element,

the first input of which is connected to the output of the first bit of the shift register, with the first control input of the additional switch and with the charge of the third pulse counter, the outputs of which are connected to the combined corresponding signal inputs of the additional switch and remote control unit, the control input of which is connected to the output of the eighth bit of the shift register, the output of the third bit of which is coincident with the third input of the third OR element and with the second control input of the additional switch, corresponds to e vyhodal and inputs which are connected respectively to constant udravleni sensor outputs and Correspondingly-vuyut1dami common multiplexer control input, wherein z has a value of 5 to 9. OT.

1 The invention relates to an elektrog communication and can be used in the construction of discrete information transmission systems.

A device for measuring the error grouping indicator in a discrete communication channel is known, comprising a series-connected phasing unit, whose input is the signal input of the device, a reference signal sensor, and a comparison unit, the second input of which is combined with the input of the phasing unit, serially connected operation mode switch, the first input of which is the input of clock pulses, the first divider, the first trigger and the first counter of the distorted blocks, the time counter, the error counter, the decoder, the control The trigger switch, the shift register, the display unit, and the first and second elements I 1.

A disadvantage of the known device is the low accuracy of measurement of the grouping index, since it is determined with a single value of the block length.

The purpose of the invention is to improve the accuracy of measurements of the error grouping indicator in a discrete communication channel.

To achieve this goal, a device for measuring the error grouping indicator into a discrete discrete; a communication channel containing a series-connected phasing unit, the input of which is the signal input of the device, the reference signal sensor and the comparison unit, the second

the input of which is combined with the input of the phasing unit, serially connected operation mode switches, the first input of which is the clock input, the first divider, the first trigger and the first counter of the distorted blocks, time counter; ph, error counter, decoder, control trigger, shift register , the display unit and the first and second elements And, introduced dividers from the second to

r-s, triggers from the second to the r-and, counters of the distorted blocks with vschkryy on u, and f +1 multiplexers counters, common multiplexer, computing unit, generator of control 1 impulses, first, second and third elements OR, key, an additional switch, the first, second and third pulse counters, a control constant sensor, a memory unit, an additional shift register, a signal combiner, and an indicator of the end of the computations, the output of the comparison unit being connected to the second input of the operating mode switch, the first output of which n with the combined inputs of the dividers and with the input of the time counter, the output of which is connected to the input of the generator of control pulses, with the installation input of the control of its trigger and the control input of the mode switch, the second output of which is connected to the input of the error counter and with the integrated installation inputs flip-flops, a reset input and an output of kg1 each of which are connected respectively to the output of the corresponding divider and to the ENTRANCE corresponding to all of the counter of the skid blocks, the output of each of which and the output of the counter osh The side is connected to the input of the corresponding multiplexer of the counter, the outputs of which are connected to the corresponding codes of the existing multiplexer, whose outputs are connected to the corresponding decoder, the outputs of which are connected to the corresponding inputs of the computing unit, the outputs of which are connected to the corresponding inputs of the display unit, the first output of the control unit pulses through a key connected to the input of the first counter pulse outputs of which are connected to the combined corresponding inputs multiplex xorov counters, and the second output of the control generator is connected to the clock inputs of the shift register and the additional shift register and to the reset input of the control trigger, the output of which through the first OR element is connected to the input of the shift register, the output of which is connected to the combined first the inputs of the first and second elements I and with the input of the addition of the computing unit, the corresponding inputs of which are connected to the outputs of the signal combining unit whose inputs are connected to the corresponding outputs of the block and with the outputs of the corresponding bits, the shift register and the additional shift register, the output and recording entry of which are connected respectively to the input of the end of calculation indicator and to the output of the first element I, the second input of which is connected to the direct output of the second pulse counter, the inverse output and the input of which is connected respectively to the second input of the second element AND, the output of which is connected to the second input of the first element OR, and to the output of the ninth digit of the shift register, the output of the second and fourth bits The first is connected to the first and second inputs of the second OR element, the output of which is connected to the first control input of the key, the second control input of which is connected to the output of the third OR element, the first input of which is connected to the output of the first digit of the shift register, with the first y. the control input of the additional switch and the input of the third pulse counter, the outputs of which are connected to the combined corresponding signal inputs of the additional switch and the memory block, the control input of which is connected to the output The eighth bit of the eighth shift register, the third bit output of which is connected to the second input of the third OR element and to the second control input of the additional switch, the corresponding inputs and outputs of which are connected respectively to the outputs of the control constant sensor and the corresponding control inputs of the common multiplexer, takes values from 5 to 9.. The drawing shows the structural electrical circuit of the device for measuring the error grouping indicator in a discrete communication channel. The device contains a control trigger 1, the first element / OR 2, a phase 3 unit, a sensor 4 reference signals, a comparison unit 5, an operation mode switch b, a time counter 7, dividers, triggers, distorted block counters, an error counter 11, multiplexers, counters, control pulse generator 13, key 14, second and third elements OR 15 and 16, first, second and third counters 17, 18 and 19 pulses, auxiliary switch 20, control constant sensor 21, memory block 22, common multi plexer 23, decoder 24, block 25 calculations, block 2. 6 injections, the signal combining unit 27, the indicator 28 of the end of the calculations, the first and the second elements AND 30, the shift register 31 and the additional shift register 32 with bits, respectively 31. The device works as follows. By the time the measurement started, the signal input and the clock input of the device are connected to the output of the discrete communication channel. All the triggers and counters of the device are in the state O. Information signals using the phasing unit 3, which extracts the synchronization combinational data from the incoming information, phases the sensor 4, the block 5 performs a bitwise comparison of the reference signals coming from the sensor 4 input sequence. The result of the comparison is the error stream, which is fed to the switch 6. At the other input of this switch, the clock pulses go along with the error stream. The device works in two stages. In the first stage, the channel is measured; it lasts a certain time, called a session. The duration of the session is determined by the speed of the discrete channel and the capacity of the counter 7. In the second stage, the calculation of the grouping indicator is performed. The computation time depends on the speed of the block. 25 computations applied by the microcircuit are determined by the generator 13 of control pulses. The measurement session begins by closing switch 6 (by the operator or

automatically), while the flow (error corresponds to signal 1) goes to the inputs 5 of the flip-flops 9;, - 9 and to the input of the counter 11, clock pulses whose period is equal to the duration of one bit of information - to the inputs of the counter 7 and dividers 8 -8 ,. The first error triggers 9 are set to 1, and the pulses from the outputs of these triggers counters 10, IO ,, are set to state 1. Counter 11 is also set to state 1 directly by an error pulse. The following noToka sadibs that arrive at the inputs S of the flip-flops 9 do not have they are acted upon and, therefore, have no effect on counters 10, since the triggers are already in state 1. This will be until such time as the triggers 9 are switched to state O. Such a translation is also carried out by pulses with outputs of dividers 8, since inputs of these dividers receives clock pulses on the exhibit at their outputs with with periods p, p,. about. , n f, bits, equal to the division factors of the dividers. After trigger 9 is reset to state O, the error cH arrives

your will translate it into a state

and,

 thirty

consequently, the counter will be set to state 2, which means that two distorted blocks in the counter are registered in counter 10. Since the division factors of dividers are chosen from the conditions of the Pa p. | , p (for example, p 10, ..., fOO, p 300, Pj 1000, etc.), the numbers of distorted blocks accumulated in the counters 10 will be different. Thus, during the session (for the 40 closed state of the switch b) in the counters 10., information will be accumulated on the number (in the binary-decimal code) of the distorted blocks of length n, П2, ..., п (the numbers d, dj, .... o d) 45, respectively. Counter 11 will accumulate the total number ibec in session d (.. This digital data is held in the counters until the end of the calculation of the grouping index ct.: CQ number of sessions is determined by the capacity of the counter 7, which receives sync pulses at its input, and is equal to-sec seconds where T is the bit duration (the period of the clock pulses), L is the capacity of the counter 7. After the counter 7 is filled, the pulse at which the switch b turns off at its output, the measurement ends. A pulse from the output of the counter 7 besides 60 dits per day tvie steering pulse generator 13 and uprav kiy trigger 1 is transferred to state 1. The operation of the two circuit elements etMh starts calculating index Group 5

feasting ftt. It is advisable to divide the operation of the device in the calculation mode into cycles.

1st cycle - calculation - l,

eo (a., / cL) 2nd cycle - calculation oL ,, °. V

2

 cycle - calculation -, (oMg)

 Cpr

last

cycle- calculation

%

),

where g - the number of gradations of the length of the block g.

The blocks, which basically {determine the operation of the device in the calculation mode, are the shift register 31 and the additional shift register 32. In the initial state, all bits of the register are in the O state. At the beginning of the calculation process, the first bit 31 goes to the state 1. Later, 1 moves along the register, while at this moment only one bit is in state 1. Promotion 1 in the register is produced under the influence of pulses produced by the generator 13. Register bits 31 are used in 1-o ..., g-ohms cycles. In the last cycle, register bits 32 are used repeatedly.

At the beginning of the first cycle, trigger 1 is transferred to state 1 and generator 13 starts operating. This generator at the first output generates pulses of pulses, the number of which in one burst is equal to the number of decimal places of counters 10 and 11. At the second output, single pulses are generated, - between packs. 1 from the trigger output 1 through the open element 2 OR is fed to the input of the register 31. The pulse from the second output of the generator 13, bit 31 will be transferred to 1, and the trigger 1 to O. The key from the output of the bit 31 will be closed through the element OR 16 The pulses from the first output of the generator 13 will begin to flow into the counter 17. In addition, the pulse from the output of the discharge 31 will go to the counting input of the counter 19, and will also switch an additional switch

20, connecting the common multiplexer 23 control inputs to the sensor output

21. The capacity of the counter 17 is determined

The number of decimal points is 1, the pin count of counters 10 and 11. For example, let us assume that the number of bits in these counters is set to 8. Then counter 17 should be executed as a binary counter for 3 bits (). The output of it in this case will be fulfilled in the form of three chains - one bt each of the discharge. These circuits are connected to the control inputs of the multiplexers 12, which are used to connect one of the eight bits of each of the counters 10 and 11 to the outputs of the multiplexers 12 (consisting of four circuits). The sequential selection of the 1st, 2nd, 3rd, ..., 8th bits for their transfer to the multiplexer 23 and further to the decoder 24 and the calculation unit 25 is performed by changing the state of the counter 17 in sequence from 1 to 8. To do this, it is necessary to feed 8 pulses in succession to its counting input, from generator 13 through key 14. Mulgiekleser 23 is designed to connect any of the input groups of circuits, each of which consists of chetfu.x circuits, with an output group, from 4 chains connected to the input of the diiifrarator 24. Selection of the group is carried out by a chain control multiplexer 23, the signals for which are produced by sensor 21 (if the additional switch 20 is in the right position in the drawing) or BINARY counter 19 (if the additional switch 20 is in the left position) If the control circuits of the multiplexer 23 receive the control signals from sensor 21, then multiplexers 12 and 23 form a chain of forwarding signals from counter 11 to the decoder 24 and further to block 25 of the calculations. If control signals are received from counter 19, a signal transfer circuit from counters 10 is formed at the considered moment (bit 31) in state 1) switch 20 in the right position, counter 17 in state 1. Consequently, with multiplexers 12 ,,, and 23, the first bit of counter 11 is transmitted via a decoder to a calculation unit. When the second pulse arrives at the counter 17, the second discharge of the counter 11 is sent to the computing unit. Further, the remaining bits of the number stored in the counter 11 are successively sent. This means that a number is entered in the memory of the computing unit 25. Since the digits (0-9) in block 25 are entered using the wire-a principle, a decoder 24 is provided for converting the binary-decimal code to decimal. In addition to the figures, commands are entered into the block 25 for the calculation of individual chains; division (-), function (F), logarithm (Ig), memory with addition (), extraction from memory and equals (PI),. com ((). The listed input circuits of the computing unit 25 are respectively indicated in the drawing. In the case when numbers or commands must be entered from different sources, a signal combining unit 27 is provided.

After entering the number d, the second clock pulse from the generator .13 will arrive at the clock input of the register 31. Bit 312 goes to state .1, impulse

from its output, the key 14 will be open, at the same time with this impulse, via block 27, the division command (g) will be entered in block 25 calculation. The third pulse in the advance circuit (at the clock input) of register 31 state 1 accepts bit 31. J. As a result, key 14 will be closed. Additional switch 20 will go to the left position, through it from the output of counter 19 control circuits in the multiplexer 23, a circuit is formed to transfer the numbers from the counter 10 to the de-inflator 24. To the input of the counter 17 comes from the generator 13 a burst of pulses at the outputs of the counter 17 sequentially coerces the binary combinations 1,: 2, 3, ..., with the help of which in the multiplexer 12. ., chains are sequentially formed L values of the transfer of all rows bit counter 10 through multiplexer 23 and decoder 24 in the computing unit 25. Thus, in block 25, the number d will be entered. Following a pulse in the chain of advance of the register, the state will accept bit 31d. Key 14 opens in the block 25 calculations will be entered command PI. Next, state 1 will receive bit 31, with E9OM, command F. will be entered into block 25. Next, bit 3 will go to state 1, a command will be entered into block 25. Next, bit 31t will go to state 1, into block 25 will be entered command-division (g). Next, state 31 is switched to bit 31. A pulse from its output triggers memory block 22 to form digital values of Vgn. In this case, ot, memory block 22, is calculated at its outputs. If, for example, clause 10, block 22 will give a pulse aei to output 1 (the characteristic J g 10, the mantissa, in the fray case is equal to zero). The choice of one of the t logarithms (constants) that are stored in memory block 22 is performed from the outputs of counter 19 in the same way that common multiplexer 23 is controlled. The state layer of multiplexer 23 when controlled from counter 19 is equal to r 22 memory unit is also equal to r. After entering the digital

The values of Ign, the size of 31g of register 31 will go to state 1. Impulse. from the output of the discharge Slj will go to the counting input of the counter 18 and transfer it to the state 1. Since the counter 18 has, direct and inverse outputs, which are connected to the inputs of the elements And 29 and 30, respectively, the state of these outputs in this The case does not change (it changes when counter 18 is in state r). The state of 1 bit Big is transmitted through the element AND 30 and eleHiTH OR. 2 to the input of the register 31. Will

(The secondary triggering circuit of the 31st register is registered. The bit 31.0 will go to state 1, KOMaHija will be entered in block 25. The bit will go to state 1, the F command will be entered in block 25. Bit 31,, rj the command P + will be entered in state 25. Simultaneously 1 will go through element 30 and element OR 2 to the input of register 31. This will re-prepare the shortcut to trigger the bit 31 of the register. This completes the 1st calculation cycle as a result of which the computation unit 25 calculates the value of оС, it is transferred to the memory of block 25 for Use in further calculations.

The next impulse from the second output of the generator 13 will be transferred to 1 bit 31. The second calculation cycle will start, which differs from the first state of the counters 18 and 19. The counter 19 will impulse from the output of the bit 31 to the state 2, this will be The ability to transfer information (number d) from counter 102 (instead of 10

I first cycle). By changing the state of the counter 19, in addition, a new logarithm value will be prepared in memory block 22. Counter 18 will also go to state 2, but its output will remain unchanged. The rest of the device in the second will work the same as in the first. As a result of the calculation, the value will be calculated

.chkju

06,

h 5

it will be entered into the memory of block 25, where it is summed up with ° C, i.e. in memory (Elok 25 will be stored oCi, + S Similarly, in cycles 3, ..., OM will be calculated ot, ... d), and 33 will be entered into memory by enclosing

B1 + оС2-ю6з ...- Ю4р,

In the b-th cycle, the counter 18 will go over to the state h, at its direct output it will turn out 1, and on the inverse O. C result when switching to 1 bit 31 and ™ the circuit is prepared for the operation of the .32 bit ,, (and not 31 ,, as it was in 1, 2, 3, ..., h -1 cycles) the r-cycle ends.

In the last cycle, after the triggering of bit 31 /., bit 32 is triggered, command F is entered into block 25 of calculations. Next goes to bit 322, and PI command is entered into block 25. Next, in 1, the bit 32 goes into unit 25 and a command is entered. Further, bit 1 goes into 1, a number equal to T is entered in block 25; Next in. 1 goes to bit 32 5, in block 25 ate e efli, a command is entered. At the same time, the end of calculation indicator 28 lights up. The last calculation cycle is complete. . it contains the final calculation:

et jW, -otg-1-otj-f ... “ci.

The result of the calculation is carried out in the nazal display of the display unit 26.

The technical and economic efficiency of the proposed device consists in increasing the accuracy of measuring the error grouping indicator.

Claims (1)

DEVICE FOR MEASURING INDEX OF ERROR GROUPING IN A DISCRETE COMMUNICATION CHANNEL, comprising, in series, a phasing unit ¹ , the input of which is a signal input of the device, a reference signal sensor and a comparison unit, the second input of which is combined with the input of the phasing unit, the operation mode switch connected in series, whose first input is an input of clock pulses, a first divider, a first trigger and a first counter of distorted blocks, a time counter, an error counter, a decoder, a control t a trigger, a shift register, an indication unit, and the first and second AND elements, characterized in that, in order to increase the measurement accuracy, 'dividers from the second to the Gth are introduced into it, triggers from the second to the gth; counters of distorted blocks from the second to the rth, r + 1 counter multiplexers, common multiplexer, calculation unit, control pulse generator, first, second and third elements OR, key, additional switch, first, second and third pulse counters, constant sensor a control unit, a memory unit, an additional shift register, a signal combining unit and an end of calculation indicator, the output of the comparison unit being connected to the second input of the operating mode switch, the first output of which is connected to the combined inputs of the divider th and with the input of the time counter, the output of which is connected to the input of the control pulse generator, with the installation input of the control trigger and with the control input of the operating mode switch, the second output of which is connected to the input of the error counter and with the combined installation inputs of the triggers, reset input and output of each which are connected respectively with dahog. the house of the corresponding divider and with the input of the corresponding counter of distorted blocks, the output of each of the κο-jg and the output of the error counter are connected to the input of the corresponding multiplexer of the counter, the outputs of which are connected to the corresponding inputs of the common multiplexer, the outputs of which are connected to the corresponding inputs - § by the ladder of the decoder, the outputs of which are connected to the corresponding inputs of the computing unit, the outputs of which are connected to the corresponding inputs of the display unit, the first output of the control pulse generator in through a key is connected to the input of the first pulse counter, the outputs of which are connected to the combined corresponding inputs of the counter multiplexers, and the second output of the control pulse generator is connected to the clock inputs of the shift register and the additional shift register and to the reset input of the control trigger, the output of which is through the first element OR is connected to the input of the shift register entry, the output of which is connected to the combined first inputs of the first and second elements AND and to the input of the addition of the calculation unit, corresponding to the input inputs of which are connected to the outputs of the signal combining unit, the inputs of which are connected to the corresponding outputs of the memory block 1016845 and to the outputs of the corresponding bits of the shift register 'and the additional shift register, the output and recording input of which are connected respectively to the input of the indicator of the end of calculations and to the outputs of the first AND element , the second input of which is connected to the direct output of the second pulse counter, the inverse output and the input of which are connected respectively to the second input of the second element And, the output of which is single with the second input of the first OR element, and with the output of the ninth bit of the shift register, the outputs of the second and fourth bits of which are connected to the first and second inputs of the second OR element, the output of which is connected to the first control input of the key, the second control input of which is connected to the output of the third element OR, the first input of which is connected to the output of the first digit of the shift register, with the first control input up to an additional switch · and with a third pulse counter, the outputs of which are connected to corresponding signal inputs of the additional switch and the memory block, the control input of which is connected to the output of the eighth bit of the shift register, the output of the third bit of which is connected to the second input of the third OR element and to the second control inputs of the additional switch, the corresponding inputs and outputs of which are connected respectively to the outputs of the sensor control constants and with the corresponding control inputs of the common multiplexer, and r takes values from 5 to 9.