SU744677A1 - Device for counting the quantity of objects of equal mass - Google Patents

Description

PCB memory block, the fourth input of which is connected to the output of the divider and c, the input of the second element OR ,. the switch is connected to the second indicator and to the input of the encoder, and the inputs of the fill mapper selection unit are connected via the third meter to the third indicator, in addition, the memory block contains the first military counter, the OR element, the overwriting element., the lock element, the second binary the counter and the fixation element the output of the delay element is connected to one of the inputs of the OR element, the output of which. connected to the input of the first binary counter, the outputs of which are connected to the inputs of the rewriting element, the outputs of which are connected to the inputs of the second binary counter, the output of which is connected to the fixation element, binary counters, the OR element, the rewriting unit and the delay element. connected to the corresponding inputs of the memory block and the output of the fixing unit is connected to the output of the memory unit. Moreover, the block for selecting the fill bit contains. element And and consistently. the connected element OR, the binary counter and the decoder, the outputs of which are connected to the element AND, the elements AND and OR are connected to the corresponding inputs of the block for selecting the filled route, the output of which is connected to the outputs of the element I.

The fill bit selection block is designed as a binary counter, the counting input of which is connected to the output of the OR circuit, the outputs of the binary counter are connected to the inputs of the decoder, the outputs of which are connected to the inputs of the AND circuits having a common bus. FIG. 1 shows a block diagram of the device, FIG. 2 is a block diagram of the memory block in FIG. 3 is a block diagram of a block for selecting a fill bit.

The device contains a weight sensor 1, a weight converter 2 of the batch of objects into a proportional number of pulses, a control unit 3, the first counter. 4 masses of a batch of objects, the first indicator 5 of the mass of the ffapTHk items, the first element b OR, the second counter 7, the decoder 8, the switch 9 specifying the mass of one object, the second Tomass indicator of one object, the block 11 for selecting the filled bit, block 12 comparison block 13 memory ti, the third counter, the number of 14 preforms in the batch, the second element 15 OR, the divisor 16, the third indicator 17 of the number of items in the batch, the first binary counter 18

tatka division (Fig. 2), element 19 OR, element 20 p6p for the first recording. Element 21 of the delay, second

log-on subtraction counter 22 of the memorized and C of the remainder, fixation element 23, OR element 24 (fig. 3), binary counter 25, decoder 26, element 27 And, I have a common bus 28.

The device works in the following way.

By means of switch 9, the mass value of one object is set. From the encoder 8, the corresponding number of pulses is fed to the input of the block 11 for selecting the filled bit, on arrival of which the bit of the third counter 14 is selected, which will be recorded during the first division cycle. A batch of items, the number of which must be determined, is placed on the weight sensor 1. The force created by the mass of objects is transmitted to converter 2, which converts this force into a proportional number of impulses supplied to the control unit 3. From which the impulses go to the first account, 4 the mass of the batch of objects and the input of the first element b OR, and from the second output of the element 6 OR to the input of the second counter 7 and to one of the inputs of the memory unit 13, which calculates and stores the remainder of the division to an integer number proportional to the mass of the party of objects to the number corresponding to the mass of one object. Block 12 compares the encoder 8 with the number from switch 9 and the increasing number from the second counter 7. If the numbers supplied to comparison block 12 are equal, the last generates a pulse coming through block 11 for selecting the filled bit to the input of the decade corresponding to the selected discharge the third counter of the 14 items in a batch.

At the same time, the same impulse from the comparison unit, the passage through the elements 15 OR, sets the second counter 7 to the zero state and is fed to the input of the block 13 of the memory. As the pulses are received from the transducer 2, the masses of the batch of objects all the described operations are repeated. After the end of the weighing of the batch of objects, the control unit 3 stops the pulses from entering the first counter 4 of the mass of the batch of objects, b element OR and memory block 13, then to another input of memory block 13, to the input of block 11 for selecting the filled bit and through the element 15 OR a common bus of the second counter 7 receives a pulse from the output of the control unit 3. Upon the arrival of this pulse, the second counter, 7, is zeroed, in block 13 of the memory, the necessary operations are carried out, after which

it remembers the remainder of dividing a number equal to the mass of a batch of objects by a number equal to the mass of one object to integers. The number of masses of a mass of one object is chosen such that after the end of the first division cycle, for: 1); the end of the weighing of the mass of batches of objects, the number of pulses passed to the input of the block 11 for selecting the fill bit from the comparison block 12, does not exceed ten with the maximum permissible mass of the batch of objects. Thus, in the initially selected bit of the third counter 14, the result of the division to Target will be recorded. If more than ten pulses arrive, the transfer unit will go to the highest bit of the third counter 14. After the pulse specified by it from the control unit 3 arrives at the input of the selection unit 11 The third digit 14 is selected one bit less than the previous one, which will be recorded in the next division cycle. After the time required for the operation of the memory unit 13, the pulses with the frequency fij start to enter the cyclic counter 7 and the input of the memory unit 13 through the second element 15 OR. At the same time, pulses with a frequency of f / 10 are sent to the other input of the memory block 13 through the divider 16. As the pulses arrive at the input of the second counter 7, the comparison unit 12 pulses the equality of two numbers at its inputs and the device operates in the same way. After entering through the divider 1b, the number of pulses equal to the remainder of the previous division is received from divider 1b the output to the control unit 3 receives a pulse, the arrival of which stops the flow of pulses with a frequency f to the input of element 6 OR and the input of the divider 16. The second division cycle is completed. As a result, due to the multiplicity of frequencies of 1:10, the separation of the residual from the previous DELAIN fIto the whole, multiplied by 10, by a number equal to the mass of one part is realized. The division also produced doceles. Further, division cycles are performed until the last bit of the third counter 14 is filled with rounding off the remainder of the last division, after which the result of the division is indicated by the third indicator 17 of the number of items in the batch. The operation of the memory unit 13 is carried out as follows (see FIG. 2). In the first division cycle, a number is supplied to the input of the binary counter 18 calculation of the remainder of the division; impulses, corresponding to a mass of a batch of objects. Simultaneously, pulses are received from the comparison unit 12, which, passing through the elements 19 OR, reset the counter 18 to O. After the termination of the arrival of the pulses to the input of the first binary counter 18 to the input of the delay circuit 21 and the common bus of the block 20 the control receives a pulse, with the receipt of which the contents of counter 18 are overwritten into the second binary counter 22, and the counter 18 after the delay time is reset to eO. At the time the pulses arrive at the input of counter 18, it will record the current from the dots up to an integer corresponding to the mass of a batch of objects) to a number corresponding to the mass of one object. Thus, in counter 22, the remainder of the division to the integer in the previous cycle will be recorded. After that, pulses of frequency f begin to arrive at the input of counter 18, and impulses with a frequency of f / lO arrive simultaneously at the input of the second binary GCchetchyk 22. The arrival of pulses continues until the number of pulses arrives at the input of binary counters 22, equal to the residual from the previous division. After that, the counter 22 is zeroed out and from the output of the zeroing clamping element 23 to the control unit 3 a pulse will be received after which the flow of pulses into the sixth two double counters 18 and 22 will stop. At this point, the counter 18 will record the remainder of the division. The operation of the device in subsequent division cycles is similar. The operation of the block for selecting the filled time is performed by her way (see Fig. 3). During the accumulation of the mass of one predetermined one input of element 24 OR, impulses are received from the meta 8 of the Encoder 8, the number of which is equal to a comma in the number corresponding to the mass of one object. These pulses travel to counter 25. The number recorded in counter 25 is de-corrupted by decoder 26, at one of the outputs of which a unit level appears: while in all others there is a zero level. Thereby, permission is given for the passage of the DYMYYUYSv, pushed onto the common bus 28 of the element 27 And from the comparison block 12, through the AND element, at the second input of which the resolving level is set with the Decoder 26. Each of the elements 27 And serves one of the bits of the third quater 14 Items in the artery, in KOT0r & iDedets mpUL1 & sOvY vbbda bloGa 12 sraGvneni. Thus, after a set of masses of one item is selected

the third counter 14, which will be recorded the results of the first cycle-division. At the end of the first division cycle, another input of element 24 OR impulse is received, which passes into counter 25, and therefore a single level occurs at another output of decoder 26. Accordingly, another of elements 27 And will open and input pulses will pass to another the bit of the counter 14. After filling the low bit of the third counter 14, rounding off the last residue, the flow of pulses to the input element OR 24 stops.

Claims (2)

1. A device for counting the number of items of equal weight, containing in series a weight sensor and a transducer connected to the control unit, a switch and counters, which are rotated in order to improve the accuracy, speed and reliability of the device , the OR elements, the avi block C1, the divider are filled, the block for selecting the fill bit, the Psytil block and the indicators, the output of the control block is connected to the input of the first element OR, with one of the outputs of the second element OR, with the input of the divider, with the first inputmemory and with the first input of the block of selection of the filled bit and with the input of the first counter, the output of which is connected to the first indicator The output of the first element OR is connected to the VTO1ILM input of the memory, and with one of the inputs of the second counter, the other input of which is connected to another output of the second element OR and outputs to one group of inputs of the comparison unit; another group of inputs of which is connected to the group of outputs of the encoder, the output of which is connected to the second input of the block the selection of the filled bit, the third input of which is connected to the output of the comparison unit, with the third input of the memory unit, the fourth input of which is connected to the output of the divider and to the input of the second element OR, the switch is connected to the second indicator and to the input of the encoder, and the outputs of the selection unit the filled bit through the third counter is connected to the third indicator. 2. The device according to claim 1, that is, the memory block contains the first binary counter, the OR element, the rewriting element, the delay element, the second binary counter and the latching element the output of the delay element is connected to one of the inputs of the OR element, the output of which is connected to one of the inputs of the first binary counter, the outputs of which are connected to the inputs of the rewriting element, the outputs of which are connected to the inputs of the second binary counter, the output of which is connected to the fixation element, the other inputs of binary counters, the OR element, the rewriting unit and the delay element are connected to the corresponding inputs of the memory unit, and the output of the fixation unit is connected to the output of the memory unit. 3, the device according to claim 1, characterized in that the block for selecting the fill bit contains an AND element and a series OR element, a binary counter and a decoder, the output of which connected to the element AND, the elements AND and OR are connected to the corresponding inputs of the block for selecting the filled route, the output of which is connected to the outputs of the element I. Sources of information taken during the examination 1. US patent 3552511, cl. 177-1, 03/10/74. 2.Patent UK  1272293, class G 01 G 19 / 42,10.08.7 -sWiSv -ty -. one