SU474760A1 - Digital frequency meter with automatic measurement range selection - Google Patents

Description

FIELD: electrical engineering; electric technology; and can be used for. Iovi-Sheni accuracy and speed of digital frequency meters.

A well-known digital meter with an automatic selection of measurement limits, containing an input illumination shaper, connected to a decimal pulse counter via a time selector, the control input of which is connected to the output of the trigger for triggering, the CTBio output device, and the format connected to the outputs of the counter, and a 13-kilogram. the older bit of the counter, and the generator of the reference time interval, connected to the input of the former for a series of reference intervals increasing in time.

The proposed frequency meter differs from the known ones in that it is equipped with a control trigger, a state decoder of "1 last and 9 preloaded digits of the counter, and a block forming a number of exemplary time intervals (the first term is equal to the minimum measurement time, the second is nine times longer first, and each of the subsequent rashen predushidvmu, increased ten times), formed by a shear repistor, a ruler of decadal dividers often followed by pulsos, two schemes

"OR," And and the pulse-: circuit: Allen keys, the inputs of which are connected to the outputs of the register and frequency dividers, and the outputs - to the inputs of the first circuit

“OR, the output connected to the First input of the second circuit“ OR and the first input of the circuit “I. (The OUTPUT of which is associated with the prohibiting input of the form; the trigger trigger, and the second input — with the iBTopbiiM input of the second circuit.

“OR (AND the output of the control trigger, the first one (INPUT is connected to the output of the forming trigger, and the second is connected to the output of the decoder, the output of the start trigger is connected to the enable input of the forming trigger, resetting input 1 of the first frequency divider and inputs c6poica in “On the rest of the cases of frequency telles, and the output (Second circuit“ OR conn.) is counted to the input of the register.

Such a design allows to increase its accuracy and speed.

The drawing shows a block diagram of the proposed device.

The device consists of an input pulse driver /, time selector 2, a decimal counter; pulses 3, a forming trigger 4, a control trigger 5, a decoder 6 of the state of the last one and of the last second to last digit of the counter 3, the trigger of memory 1 of 1 older bit

the counter 3, the block of formation of a row and increasing. in time of the exemplary time intervals

P + 97;, + ...

edited by the shift register 5, a ruler of 9 decadal pulse-following frequency dividers, a circuit 10 of pulse-iotecial keys, the first circuit “OR / 7, a circuit“ AND 12 and a second circuit ”OR 13, the trigger trigger 14, the generator 15 of the smallest model time interval G / j and information output devices 16.

The device works in the following way.

By the Signal “Iusk trigger trigger 14, the IRIN“ clears the initial state, and in counter 3, trigger 7, and register 8, the reset to “O” occurs. The priest after Iuska Imulzul iz from the generator 15 arriving at the second input of trigger 14, causes the trigger 14. The output trigger of trigger 14 starts the forming trigger 4 and resets the dividers of the ruler I, and the first divider is entered, 1, and the rest - "ABOUT. The output switch 4 of the trigger 4 opens the selector 2, II to the counter 3, the driver / enters the input frequency. By the same impulse, trigger 5 is set / injected into a state in which its output closes the state circuit 12 and enters "1 by means of the scheme OR 13, into the first register bit of the register 8. As a result, the impulse and theoretical key of circuit 10 connected with this bit of doM, it turns out to be open on the second run of the IM generator of the generator 15 passes through this key to the output cxeiMbi OR 1.1. Thus, the first model Interval of time (first limit) G /, is formed. If the circuit "And 12 is closed by the control rpinirreipoM 5, the output and the pulse of the circuit OR // not (passes to its output and does not transfer the trigger 4. The counting of the input frequency pulses continues at the second limit. The output pulse of the circuit 11 through the circuit" OR in register 8 transfers the "1 to the next bit, opening the following to them: zero it-.potential | TSN1alny key 1circuit 10. After the arrival on the first divider of the ruler-and 9 nine IM1pulsovv IC period of the TC at its output appears im.1pul zs second (limit, which through the open second imtulno-potential) key circuit 10 passes to the output circuit 11. The second limit is equal to 10 T.

If the y1dp1 trigger 5 (Continues to hold circuit 12 in the closedO) M state, the input frequency pulse counting continues, and the second limit pulse through the circuit / produces in the register S.transfer "1 to the third bit, opening the third pulse of the potential-negative potential circuit 10. If immediately after the end of the second-momentum Pulse, the decades of counter 3 are filled to the state 19000. .. then the decoder 6 is triggered and the control trigger 5 is thrown,

which opens circuit 12. Since the pulse of the second limit passed through how c & 12 was opened, the counting continues until the pulse of the third limit is received, while the tenth counter 3 replenishes, sets to 1 trigger 7 and continues counting. Counter 3 is in (full to some state, but it does not overrun, since and. The third limit pulse M1 flips trigger 4, selector 2 closes and the pulse count stops 1s.

For values of frequencies greater than 1 10 measurements, it is set such that "1 high-order bit is always in trigger 7, at frequencies slightly less than 1-10, the Brace of measurement is stabilized by the same M, and the information is in counter 3. At In this way, the measurement error does not change.

The process of measuring the frequency and the process of determining the measurement time occur simultaneously, this three sigma; it is not the overflow of the meter that triggers the determination of the measurement time, but its intermediate state, chosen in such a way that the measurement of frequencies that are multiples of 1 IC, occurs with the maximum | frequency meter accuracy and without loss of information.

Subject matter

Digital frequency meter with automatic selection of measurement limits, containing an input pulse shaper connected to a decimal pulse counter via a variable selector, the control input of which is connected to the output of the forming trigger, a trigger trigger, an information output device connected to the outputs of the counter and memory trigger "1 older bit

counter, and a model time interval generator, connected to the input of a number of formers (Time-increasing exemplary inter) shafts of time, characterized in that, in order to improve accuracy and speed, it is equipped with a control trigger, the last one and " 9 pre-discharge bits of the counter and a block forming a number of exemplary time intervals (the first term is equal to the minimum time of measurement, the second is nine times the first, and each of the following is equal to the previous one, increased by ten times), sample anyoto with a move register, a ruler of decadal frequency dividers

following impulses, two schemes “OR, scheme“ AND ”and a scheme of impulse-numerical keys, the INPUTS of which 1 are connected to the output of the register and frequency dividers, and the exits to the inputs of the first“ OR ”output connected to the first input of the second“ OR and the first input of the AND circuit, the output of which is associated with the inhibitory input of the forming trigger, and the second input - with the second input of the second circuit 1 "OR and the output of the control trigger, the first input of which is connected to the output of the forming trigger, and the second output of decoder, wh.m trigger output trigger is connected to the permissive input of the form, its trigger, input

reset in “1 the first frequency divider and the reset inputs in“ About the other frequency dividers, and the output of the second circuit “OR connected to the input of the register.