SU1085012A1 - Device for demodulating binary signals - Google Patents

Abstract

A DEVICE FOR DEMODULATION. BINARY SIGNALS containing an adder, the output of which is connected through series-connected discriminator of the level and the key to the input of the relay, which is connected to the shift register register, the outputs of which are. They are connected to the first inputs of the signal processing channels, the second inputs of which are connected to the corresponding outputs of the input signal converter, the totalizer inputs connected to the outputs of the signal processing channels, each of which contains a delay line, the first output of which is connected to the input of the impulse response estimator, outputs which are connected to the first inputs of multipliers, subtractive blocks, the first inputs of which are connected to the corresponding second outputs of the delay line, the input of which is the second input The signal processing channel, the first inputs of which are the second multiplier inputs, characterized in that, in order to reduce the demodulation time, the shaper of the reference signals, the first and second computational units, the shaper of the partial sums, the shaper of the threshold signals, accumulator with accumulator, unit, control and additional subtraction unit, first, the input of which is connected to the output of the accumulator with storage, the first input of which is connected to the output of the control unit and the first input of the threshold signal generator, the second input of which is connected to the output of the partial sum generator, eg the input of which is connected to the output (L of the first computing unit, the first inputs of which are connected to the first input and inputs of the second computing unit and the primary output of the reference signal generator The inputs of which are connected to the first inputs of multipliers, the outputs of which are connected to the second inputs of the corresponding subtraction units, 00 the outputs of which are connected to the corresponding second inputs. The second computing unit, the output of which is connected to the second input of the accumulator adder, the second outputs of the reference signal generator i are connected to the second, inputs of the first computing unit, and the output of the threshold signal generator is connected to the second input of the additional subtracting unit, the output of which is output signal processing channel.

Description

The invention relates to telecommunications and can be used in systems for transmitting discrete information through communication links with intersymbol interference. A device for transmitting binary signals in a multipath communication channel is known, comprising a measurement unit for the impulse response of the channel, a reference signal generation unit, a multiplier, an integrator, and a TI register. The disadvantage of this device is low immunity. ; The closest technical solution to the invention is a device for demodulating binary signals, comprising an adder, the outputs of which are connected through a serially connected discriminator of a level and a key to a relay input, the output of which is connected to the input of a shift register, whose outputs are connected to the first inputs of signal processing channels, the second inputs of which are connected to the corresponding outputs of the input signal converter, and the inputs of the adder are connected to the outputs of the signal processing channels, each of which contains The initial delay, the first output of which is connected to the input of the impulse response estimator, whose outputs are connected to the first multiplier inputs, subtracting blocks, the first inputs of which are connected to the corresponding second outputs of the line ky, the input of which is the second input of the signal processing channel, the first inputs which are the second inputs of the multipliers 2. However, the known device has a long demodulation time of binary signals. The aim of the invention is to reduce the demodulation time. The goal is achieved by the fact that the device for demodulating binary signals contains an adder, the output of which is connected through series-connected discriminator level and key to the input of the relay, the output of which is connected to the input of the shift register, the outputs of which are connected to the first inputs of signal processing channels, the second whose inputs are connected to the corresponding; The outputs of the converter of the input signal, and the inputs of the adder are connected to the outputs of the signal processing channels, each of which contains a delay line, the first output of which is connected to the input of the impulse response estimator, the outputs of which are connected to the first inputs of the multipliers, subtracting blocks, first inputs which are connected to the corresponding second outputs of the delay line, the input of which is the second input of the signal processing channel, the first inputs of which are the second inputs of the multiplier, are entered into each signal processing channel, reference signal generator, first and second calculation blocks, partial sum generator, threshold signal generator, accumulator with accumulator, control unit and additional subtraction unit, the first input of which is connected to the output of the accumulator, the first input of which is connected to the output of the block control and with the first input of the threshold value generator, the second input of which is connected to the output of the partial sum generator, the input of which is connected to the output of the first computation unit, the first inputs of which are connected to the first inputs of the second computing unit and the first outputs of the reference signal generator, whose inputs are connected to the first inputs of the multipliers, the outputs of which are connected to the second inputs of the corresponding subtractive blocks, the outputs of which are connected to the corresponding second inputs of the second the computing unit, the output of which is connected to the second input of the accumulator adder, the second outputs of the reference signal generator being connected to the second inputs of the first calculate nogo unit and the output of the threshold signal coupled to the second input of the subtracter by the additional unit, whose output is the output of the signal processing channel. The drawing shows a structural electrical circuit of the proposed device. The device for demodulating binary signals contains an input signal converter 1, signal processing channels 2, delay line 3, impulse response estimator 4, subtracting blocks 5, a reference signal conditioner b, an additional subtraction block 7, multipliers 8, a partial summaker 9, register 10 shift, adder 11, discriminator 12 level, key 13, relay 14, first and second computational units 15 and 16, driver 17 of threshold signals, adder 18 with a drive, control unit 19. The device works as follows. The algorithm of optimal reception on the background of white noise, proposed in the known device: MinU Z (,. 5 (t -, - T) dt “, where 5 (| are reaki; and the channel for one package is positive polarity, Z (-t ) is the accepted oscillation, we transform as follows: Expanding the square, and Gatyva, that the value of 1 Z (tldt does not depend on a, and therefore, neither the combination that provides the minimum of the expression, has any effect. (1 ) can be presented in the following form: GT "G 1 GM1 (,, .xS {biT fcli M-1 Ml Z {tJ5 (ta) c3t-li: 5: a." l.2, .0 1) (t -iTlS (t-jT) clt In the case of discrete signal processing, the algorithms (1) and (2) m be written in as follows: IN g M-1 - | 21 SlvS.VJ), where N is the number of Discrete signals on the interval O - MT. jy AIVI M-1 NAIVI M-1 | -oi Vriio | o ".-" -5 kj H-1 The last expression, in view of the metric of the second term in the fig. boxes, is represented as M-1 М-1 N Ммх | 2 и. (с, .Ццо 1 Ki to triV Comparing expressions (Il and (you can see, that a device that develops an algorithm according to (. 2), has a much smaller number of operations than a device that operates according to (). Indeed, with the implementation of the algorithm according to V 2I with slow changes in the parameters of the decal karal: o-- - 515 5 6ij 1,1 k-i k-j. M: -. ri f- f: + fiiOT taki, j: 0, l ... Wl, a also .4r f) ri + 1 M Iiri + l and that to the clock cycle do not change, and therefore in their calculation on each clock cycle -there is no need. Therefore, for any fixed number M of overlapping dressings at the reception, an algorithm that implements the expression (24 requires at each processing step M.-i- multiplication and deposition operations to form. N cyMivi 51 Z, 5... where j 0,1, .. .M-1,. Cr-1 k and in addition, changes in the sign and 2 -1 addition operations to form Vri. Nor any sums as well as (M-1J 2 operations carry out the principal of all sums . "I- -j SMVi also-2. subtractions for calculating all possible values of the expression in curly brackets. In general, the device implementing the algorithm in the form 12) requires on each processing cycle with a duration of N + 1 T seconds M1 multiplication operations. 2-1 + 2 (m-1 | operations addition of subtraction. and change the sign, as well as 2 subtractions of expressions in curly brackets. The device that implements the algorithm in the form (i 1 requires on each. processing tact .H + 1 operations 2.M "4 changes in sign and addition. 2S operations of subtraction, as well as 2 N multiplications of erections in a square-). This shows that a device that implements UM requires on each tak2 those in -. ..., times less operations um-m + 1, 2, -. scimitar as the slowest. operations than a device that implements an algorithm in the form (1I. So, for example, when digitally registering these algorithms) is total, if P5 and the multiplication operation are added to addition operations, we can compare numerically both algorithms, with the maximum number of bits Q in each sample. Thus, the signal from the output of the communication channel is fed to the converter 1 of the input signal, in which the operation of sampling and analog-digital conversion is carried out. The input signal converter 1 has n outputs, where P is the frequency band of the received video signal and V is the transmission rate, square brackets mean that a fraction of the fraction is intact. From each of its outputs to the second input of the corresponding channel 2 of signal processing, samples of the signal Z (t) are received. The samples of the input signal are fed to the input of the delay line 3 after one clock interval of each channel 2 of signal processing, and then to block 4, the impulse response estimates, where SQ, 5, ..., 5 - values are formed, which are the counts of the channel response From the output of block 4, the impulse response estimates of the signal are sent to the first inputs of multipliers 8, to the second inputs of which signals + 1 are sent from the outputs of the shift register 10, and the outputs of the multipliers 8 are connected to the second inputs of the reading blocks 5, on ne The first inputs of which receive samples of the signal Z (t. Ie, at the output of subtractive blocks 5, samples of the difference signal z are formed (tI.that differ from the samples of the received signal Z {tl) by the fact that they are subtracted from all the preceding inputs, z ( (t) - as (biT). In addition, the samples from the output of block 4 estimate the impulse response to the shaper b of the reference signals, the task of which is the formation of matrix columns which; represent a set of samples of the evaluation of the response of the communication channel to a single parcel, shifted relative to each other by the interval T and limited to the same analysis interval T.MT: S, the output of the imaging unit 6 of the reference signals of the matrips and SQ - S are alternately received at the first inputs the second computational unit 16, the second inputs of which receive the values of the samples Zlt-l from the outputs of the subtracting units 5. A matrix-column is formed at the output and the matrix-column 5 is fed to the second input of the adder 18 with the accumulator, the first input of which is dinene with the output of control block 19, which gives all possible variants of binary vectors: "" 01 "1 -." M-Ji Ch.. those. we get to the output of "5 M-1 g. but. Z (t) S (4: -IT) c | -t: Simultaneously with this, the signals shifted relative to each other,. From the first and second outputs of the driver, 6 reference signals arrive at the first and second inputs of the first computational unit 15, at the output of which the elements of the square matrix of §, 5Г5 are formed. the matrix is triangular above the diagonal of 4gо5. (5; §, 1 --- (§; vJ (5,) -. (5; v.) 0 (S: -2VJ O .O which come to the input of the imager 9 partial sums the output of which forms the matrix-column X, whose elements are the sum of the elements of the rows and columns of the matrix Q with the same first, first index until reaching the diagonal / and then the second value of the same index:. (§:) Kh --- (i, «i х (5: J ---; К§ .-, №; Д KvJ (sIvJ-45« Vi)) from the output of the former 9 partial sums of matrix columns X are fed to the second input of the former 17 threshold signals, on the first entrance of which comes two vector-screw 01) and the output is on the value of M-1 A-2 N /, -i () .- .a S (t-iT) S (i-jT, lat i i: o - J....

Then, the signals from the outputs of the accumulator 18 with the accumulator and the D7 shaper of the threshold signals are fed to the inputs of the additional subtractive unit 7, the output of which is

.. and

T - - t - L I

, 5, -5 .o.Z (tl5 (b, T) climate

M-1 L1-1 ..

(Ht) dt,

l

which arrives on. one of the inputs of the adder 11, the remaining inputs of which receive the numbers from the outputs of the other similar channels 2 signal processing. From the output of adder 11, the difference value total over all n channels 2 of signal processing

enters the input of the discriminator 12 level, which selects the highest value in the entire enumerated space of possible combinations of binary vectors b. After finding the difference value, the first vector element (+1 or -1) is fed through the key 13 and the relay 14 to the input of the shift register 10 and to the device output.

The advantages of the proposed device are in reducing the demodulation time while maintaining the limiting (potential noise immunity when receiving against the background of white noise, which allows

a given amount of equipment to increase the speed of information transfer, or at a given speed to reduce the amount of equipment, which, in turn, leads to improved economic

performance and reliability.

Claims (1)

(5 7) DEVICE FOR DEMODULATION OF BINARY SIGNALS, containing an adder whose output is connected through a series-connected discriminator level and a key to the input of the relay, the output of which is connected to the input of the shift register, the outputs of which are. connected to the first inputs of the signal processing channels, the second inputs of which are connected to the corresponding outputs of the input signal converter, the adder inputs being connected to the outputs of the signal processing channels, each of which contains a delay line, the first output of which is connected to the input of the pulse response evaluation unit, the outputs which are connected to the first inputs of the multipliers, subtracting blocks, the first inputs of which are connected to the corresponding second outputs of the delay line, the input of which is the second input channel signal processing, the first inputs of which are the second inputs of the multipliers, characterized in that, in order to reduce the demodulation time, reference signal shaper, first and second computing units, partial summer, threshold signal shaper are introduced into each signal processing channel, an adder with a drive, a control unit and an additional subtracting unit, the first one whose input is connected to the output of the adder with a drive, the first input of which is connected to the output of the control unit and with the first the threshold signal conditioner, the second input of which is connected to the output of the partial summer, § whose input is connected to the output of the first computing unit, the first inputs of which are connected to the first inputs of the second computing unit and the first outputs of the "reference signal generator, the inputs of which are connected to the first inputs of the multipliers, the outputs of which are connected to the second inputs of the corresponding subtracting blocks, the outputs of which are connected to the corresponding second inputs of the second computing unit , the output of which is connected to the second input of the adder with a drive, and the second outputs of the driver of the reference signals are connected ί with the second inputs of the first calculator! block, and the output of the threshold signal generator is connected to the second input of the additional subtracting block, the output of which is the output of the signal processing channel.