SU1720165A1 - Device for receiving discrete signals in memory channels - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of reception. A device for receiving discrete signals in memory channels contains a comparison unit 1, a normalizing block 2, a control block 3, a block 4 for changing the impulse response of a communication channel, a driver 5 of the expected code sequences, adders 6 and 20, registers 7, 13, 14 and 18 signal values, key 8, encoder 9, nonlinear converter 10, switches 11 and 21. accumulating adder 12, block 15 of permanent memory, block 16 of synchronization, block 17 of searching information packets, multiplier 19. register of 22 packets, maximum selection block 23 and you a matching unit 24. The purpose of the invention is accomplished due to the absence in the apparatus predistortion signal generating circuits, the presence of which leads to erroneous decisions m when receiving signals. 1 il. 1 CO

Description

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The invention relates to telecommunications and can be used in information transmission systems.

The purpose of the invention is to increase the reliability of receiving discrete signals with ultra-precise coding.

The drawing shows a structural electrical circuit of the proposed device.

A device for receiving discrete signals in memory channels contains a comparison unit 1, a normalization unit 2, a control unit 3, a measurement channel 4 impulse response measurement unit, a driver 5 of expected code sequences, a first adder 6, a first signal value register 7, a key 8 , encoder 9, nonlinear converter 10, first switch 11, accumulating adder 12 and second and third registers 13 and 14 signal values, fixed memory block 15, synchronization block 16, block 17 of information parcels, fourth register 18 values of c I drove, a multiplier 19, a second adder 20, a second switch 21, a register 22, information packages, the selection unit 23 and the maximum matching output unit 24.

The device works as follows.

The quadrature components of the received realization of the signal x (t) are fed to the input of the measurement unit 4 and the second input of the comparison unit 1. From the output of measurement unit 4, the quadrature components of the reaction g (t) are fed to the second input of the former, the first input of which receives the code sequences of the convolutional code from the output of the encoder 9. From the output of the former, the quadrature components of the expected implementations of the signal Zx + D (t) arrive to the first input of the comparison unit 1, from the output of which the values of the distance (p or pi) are fed to the input of the normalizing unit 2, the control input of which is given a signal determining its transmission coefficient. From the output of the normalizing unit 2, the normalized distance values (-p / N0 or pi / N0) through the adder 6 are fed to the input of the nonlinear converter 10 with an exponential characteristic, from the output of which the first sequence of signal values (exp (- / 91 / M0) orexp (- / C2 / No) is fed to the input of register 14. After writing to the register 14 of the entire first sequence of signal values, the register will generate at its output a second sequence of signal values supplied to the first input

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multiplier 19, the second input of which receives an auxiliary sequence of signal values from the output of register 7. From the output of multiplier 19, a third sequence of signal values goes to the first input of the adder 20 and to the input of the accumulating adder 12. During the formation of the third sequence, the switch 21 connects the register output

0 22 to the second input of the adder 20. At the end of the formation of the third sequence in register 22, a fourth sequence of signal values will be formed, which with the help of the switch 21 is fed to the input of maximum selection unit 23, the output of which is the number of maximum signal value from the fourth sequence is fed to the input of the output matching unit 24. from the output of which the sequence B is binary

0 information symbols are provided to the recipient. From the output of the key 8 a new auxiliary sequence of signal values is fed to the input of the register 7. To the input of the encoder 9, through the register 13 is received from

5 outputs of the block 17 for iterating information parcels binary sequences, each of which is determined by the next state of the block 17 enumeration, the formation time of each of the 2

The 0 signal values from the first sequence of signal values are added up from the execution time of the following elementary operations: the change time of the state of the enumeration block 17

5 by the impact of the next pulse from the synchronization block 16, the recording time of the state of the enumeration block 17 into the register 13 and the generation of the next code sequence by the encoder 9, the time

0 the formation of quadrature components of the next expected implementation of the signal in the imaging unit 5, the computation time of the next distance in the comparison unit 1, the normalization time of the next

5 distance values in normalizing unit 2, transit time through adder 6 and nonlinear conversion, recording time of the next signal value from the first sequence to register 14. The period of the signal coming from synchronization unit 16 to input of enumeration unit 17 must be not less than generating one signal value from the first sequence. After sun

5, the first sequence of signal values is written to register 14, periodic recording is performed from register 14 to register 18 of this sequence and reading it from the output of register 18 to the first

input multiplier 19. When reading each signal value from register 18, multiplication into multiplier 1 ° 9, addition in adders 12 and 20, shift in register 22 occurs. After every 2 signal values from the third sequence from the output of multiplier 19 to input of adder 12, 8 closes and shifts the register 7, after which the accumulating adder 12 is zeroed. During the remaining part of the processing cycle after the formation of the first sequence, rewriting from register 14 to register 18 is performed once, multiplier 19 performs multiplications, adders 12 and 20 perform 2 summation operations, key 8 commutes 2 times, information shift in register 22 occurs in 2b 0 + 1 times, and in register 7 - 2b times, after which switch 21 connects the output of register 22. To the input of maximum selection block 23, a fourth sequence of signal values is fed to the input of maximum selection 23 from the output of register 22, then the course of the output block 24 is provided to the recipient with a sequence of binary information symbols. At the beginning of each processing cycle, it is necessary to set the counter 17 to the initial zero state, reset the register 22. Before the start of the (initial) processing cycle, it is necessary, besides the listed actions, to reset the accumulating adder 12 and using the switch 11 to write to the register 7 sequence 2 of the same non-zero values of the signal from the block 15 of the permanent memory. The last two operations are carried out at the time of power-up, as well as before receiving the next packet of information on the frame alignment signal (when using packet transmission),

Claims (1)

Apparatus of the Invention A device for receiving discrete signals in memory channels, comprising a nodal synchronization unit, the output of which is connected to the input of the search parcel unit, the first switch, the information send register, the output of which is connected to the input of the second switch, the maximum selection unit, the output of which is connected to the input of the output matching unit, the encoder, the output of which is connected to the first input of the driver of the expected code sequences, the output of which is connected to the first input of the unit cf The module and the measurement unit of the impulse response of the communication channel, the output of which is connected to the second input of the driver of the expected code sequences, characterized in that, in order to increase the reliability of receiving discrete signals with convolutional coding, four registers of signal values are entered into it, two adders, a key, a multiplier, an accumulating adder, a nonlinear converter, a normal unit, a control unit and a permanent memory unit, the outputs of which are connected to the signal inputs of the first switch, control Its input is connected to the first input of the accumulating adder, the output of which is connected to the input of a key, the output of which is connected to the control input of the first register of signal values and to the input of the control unit whose output is connected to the first input 5 of the first adder, the output of which is connected to the input of a nonlinear converter, the output of which is connected to the input of the third register of signal values, the outputs of which are connected to the inputs of the fourth register of signal values, the output of which is connected to the first input of the multiplier, the second input of which is connected to the output of the first value register a signal whose signal inputs are connected to the outputs of the first switch, the multiplier output is connected to the second input of the accumulating adder and to the first input of the second adder, Torah input of which is connected to the output of the second 0 of the switch, the output of which is connected to the input of the maximum selection unit, the input of the measurement unit of the impulse response of the channel is connected to the second input of the comparison unit, the output of which is connected to the input of the normal unit, the output of which is connected to the second input of the first adder; parcels connected to the inputs of the second register of signal values, the output of which 0 is connected with the input of the encoder, and the output of the second adder is connected to the input of the register of information parcels.